參數(shù)資料
型號(hào)： AD7812YRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： +2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs
中文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： TSSOP-20
文件頁(yè)數(shù)： 3/19頁(yè)
文件大?。?/td> 210K
代理商： AD7812YRU
–3–
REV. B
AD7811/AD7812
Parameter
Y Version
Unit
Test Conditions/Comments
POWER SUPPLY
V
DD
2.7
5.5
V min
V max
For Specified Performance
I
DD
Digital Inputs = 0 V or V
DD
Normal Operation
Power-Down
Full Power-Down
Partial Power-Down (Internal Ref)
Power Dissipation
Normal Operation
Auto Full Power-Down
Throughput 1 kSPS
Throughput 10 kSPS
Throughput 100 kSPS
Partial Power-Down (Internal Ref)
Full Power-Down
3.5
mA max
1
350
μ
A max
μ
A max
See Power-Up Times Section
V
DD
= 3 V
10.5
mW max
See Power vs. Throughput Section
31.5
315
3.15
1.05
3
μ
W max
μ
W max
mW max
mW max
μ
W max
NOTES
1
See Terminology.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
Parameter
Y Version
Unit
Conditions/Comments
t
POWER-UP
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
1.5
2.3
20
25
25
5
5
10
10
5
20
100
μ
s (max)
μ
s (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (min)
Power-Up Time of AD7811/AD7812 after Rising Edge of
CONVST
Conversion Time
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
RFS Rising Edge to SCLK Rising Edge Setup Time
TFS Falling Edge to SCLK Falling Edge Setup Time
SCLK Rising Edge to Data Out Valid
DIN Data Valid to SCLK Falling Edge Setup Time
DIN Data Valid after SCLK Falling Edge Hold Time
SCLK Rising Edge to D
OUT
High Impedance
DOUT High Impedance to
CONVST
Falling Edge
3
3
3
3, 4
NOTES
1
Sample tested to ensure compliance.
2
See Figures 16, 17 and 18.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V
±
10% and
0.4 V or 2 V for V
DD
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
11
, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
DD
= 2.7 V to 5.5 V, V
REF
= V
DD
[EXT] unless otherwise noted)
2.1V
200 A
C
L
50pF
I
OH
TO
OUTPUT
PIN
I
OL
200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
相關(guān)PDF資料
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