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參數(shù)資料
| 型號： | AD7799BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 3CH LP 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 470 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 3 個差分，單極；3 個差分，雙極 |
| 配用： | EVAL-AD7799EBZ-ND - BOARD EVALUATION FOR AD7799 |
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Data Sheet
AD7798/AD7799
Rev. B | Page 19 of 28
0
–20
–40
–60
–80
–100
0
3000
2500
2000
1500
1000
500
04856-015
FREQUENCY (Hz)
(dB)
Figure 14. Filter Profile with Update Rate = 242 Hz
0
–10
–20
–30
–40
–50
–60
0
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
04856-016
FREQUENCY (Hz)
(dB)
Figure 15. Filter Response with Update Rate = 470 Hz
DIGITAL INTERFACE
As previously outlined, the programmable functions of the
AD7798/AD7799 are controlled using a set of on-chip registers.
Data is written to these registers via the serial interface, which
also provides read access to the on-chip registers. All
communication with the part must start with a write to the
communication register. After power-on or reset, the device
expects a write to its communication register. The data written
to this register determines whether the next operation is a read
or write operation and to which register this operation occurs.
Therefore, write access to any register begins with a write
operation to the communication register, followed by a write to
the selected register. A read operation from any other register
(except when continuous-read mode is selected) starts with a
write to the communication register, followed by a read
operation from the selected register.
The serial interface of the AD7798/AD7799 consists of four
signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used
to transfer data into the on-chip registers, and DOUT/RDY is
used for accessing data from the on-chip registers. SCLK is the
serial clock input for the device and all data transfers (either on
DIN or DOUT/RDY) occur with respect to the SCLK signal.
The DOUT/RDY pin operates as a data ready signal, with the
line going low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of
the data register to indicate when not to read from the device to
ensure that a data read is not attempted while the register is
being updated. CS is used to select a device. It can be used to
decode the AD7798/AD7799 in systems where several
components are connected to the serial bus.
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7798/AD7799, with CS being used to decode the part.
Figure 3 shows the timing for a read operation from the
AD7798/AD7799 output shift register, and Figure 4 shows the
timing for a write operation to the input shift register. It is
possible to read the same word from the data register several
times, even though the DOUT/RDY line returns high after the
first read operation. However, care must be taken to ensure that
the read operations are complete before the next output update
occurs. In continuous-read mode, the data register can only be
read once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7798/AD7799. The end of the con-
version can be monitored using the RDY bit in the status regis-
ter. This scheme is suitable for interfacing to microcontrollers.
If CS is required as a decoding signal, it can be generated from a
port pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.
The AD7798/AD7799 can be operated with CS being used as a
frame-synchronization signal. This scheme is useful for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by CS, because CS normally occurs after the falling edge of
SCLK in DSPs. The SCLK can continue to run between data
transfers, provided that the timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7798/AD7799 line
for at least 32 serial clock cycles, the serial interface is reset.
This ensures that the interface can be reset to a known state if
the interface is lost due to a software error or a glitch in the
system. Reset returns the interface to the state in which it is
expecting a write to the communication register. This opera-
tion resets the contents of all registers to their power-on
values. Following a reset, the user should allow a period of
500 microseconds before addressing the serial interface.
The AD7798/AD7799 can be configured to continuously
convert or to perform a single conversion (See Figure 16
through Figure 18).
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