參數(shù)資料
型號(hào)： AD7795BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/37頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 6CH LOW-PWR 24TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 470
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 6 個(gè)差分，單極；6 個(gè)差分，雙極
AD7794/AD7795
Rev. D | Page 20 of 36
Table 18. Operating Modes
MD2
MD1
MD0
Mode
0
Continuous Conversion Mode (Default).
In continuous conversion mode, the ADC continuously performs conversions and places the result in the data
register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device
in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses
are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communica-
tions register. After power-on, the first conversion is available after a period of 2/fADC when chop is enabled or
1/fADC when chop is disabled. Subsequent conversions are available at a frequency of fADC with chop either
enabled or disabled.
0
1
Single Conversion Mode.
When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator
requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/fADC when
chop is enabled, or 1/fADC when chop is disabled. The conversion result is placed in the data register, RDY goes
low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains
active (low) until the data is read or another conversion is performed.
0
1
0
Idle Mode.
In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still
provided.
0
1
Power-Down Mode.
In power-down mode, all the AD7794/AD7795 circuitry is powered down including the current sources, power
switch, burnout currents, bias voltage generator, and clock circuitry.
1
0
Internal Zero-Scale Calibration.
An internal short is automatically connected to the enabled channel. A calibration takes two conversion cycles to
complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the
calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following
a calibration. The measured offset coefficient is placed in the offset register of the selected channel.
1
0
1
Internal Full-Scale Calibration.
A full-scale input voltage is automatically connected to the selected analog input for this calibration.
When the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and one
conversion cycle when chop is disabled.
For higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled
and 2 conversion cycles when chop is disabled.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is
placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register
of the selected channel.
Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system
full-scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is
changed to minimize the full-scale error.
1
0
System Zero-Scale Calibration.
User should connect the system zero-scale input to the channel input pins as selected by the CH2 bit, CH1 bit,
and CH0 bit. A system offset calibration takes two conversion cycles to complete when chop is enabled and one
conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when
the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coeffi-
cient is placed in the offset register of the selected channel.
1
System Full-Scale Calibration.
User should connect the system full-scale input to the channel input pins as selected by the CH2 bit, CH1 bit, and
CH0 bit.
A calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when
chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is
complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in
the full-scale register of the selected channel.
A full-scale calibration is required each time the gain of a channel is changed.
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