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參數(shù)資料
| 型號： | AD7791 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Buffered 24-Bit Sigma-Delta ADC |
| 中文描述： | 低功耗，緩沖24位Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 308K |
| 代理商： | AD7791 |
AD7791
Bit Location
MR3
Rev. 0 | Page 12 of 20
Bit Name
BO
Description
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal
path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled
only when the buffer is active.
Unipolar/Bipolar Bit.
Set
by user to enable unipolar coding, i.e., zero differential input will result in
0x000000 output and a full-scale differential input will result in 0xFFFFFF output.
Cleared
by the user to
enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000,
zero differential input will result in an output code of 0x800000, and a positive full-scale differential
input will result in an output code of 0xFFFFFF.
Configures the ADC for buffered or unbuffered mode of operation. If
cleared
, the ADC operates in
unbuffered mode, lowering the power consumption of the device. If
set
, the ADC operates in buffered
mode, allowing the user to place source impedances on the front end without contributing gain errors
to the system.
This bit must be programmed with a Logic 0 for correct operation.
MR2
U/B
MR1
BUF
MR0
Table 10. Operating Modes
MD1
MD0
0
0
0
Mode
Continuous Conversion Mode
(Default)
Reserved
Single Conversion Mode
Power-Down Mode
0
1
1
1
0
1
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word
rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the
filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
FR7
0(0)
FR6
0(0)
FR5
CDIV1(0)
FR4
CDIV0(0)
FR3
0(0)
FR2
FS2(1)
FR1
FS1(0)
FR0
FS0(0)
Table 11. Filter Register Bit Designations
Bit Location
Bit Name
FR7–FR6
0
FR5–FR4
CLKDIV1–
CDIV0
Description
These bits must be programmed with a Logic 0 for correct operation.
These bits are used to operate the AD7791 in the lower power modes. The clock is internally divided and
the power is reduced. In the low power modes, the update rates will scale with the clock frequency so
that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also.
00
Normal Mode
01
Clock Divided by 2
10
Clock Divided by 4
11
Clock Divided by 8
This bit must be programmed with a Logic 0 for correct operation.
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and
the noise. See Table 12, which shows the allowable update rates when normal power mode is used. In
the low power modes, the update rate is scaled with the clock frequency. For example, if the internal
clock is divided by a factor of 2, the corresponding update rates will be divided by 2 also.
FR3
FR2–FR0
0
FS2–FS0
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