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參數(shù)資料
| 型號： | AD7789BRM-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 16.6 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
AD7788/AD7789
Rev. B | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03539-005
AD7788/
AD7789
TOP VIEW
(Not to Scale)
SCLK 1
CS 2
AIN(+) 3
AIN(–) 4
REFIN(+) 5
DIN
DOUT/RDY
VDD
GND
REFIN(–)
10
9
8
7
6
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous, with all data transmitted in
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-
mitted to or from the ADC in smaller batches of data.
2
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT/RDY used to interface with the device.
3
AIN(+)
Analog Input. AIN(+) is the positive terminal of the fully differential analog input.
4
AIN()
Analog Input. AIN(–) is the negative terminal of the fully differential analog input.
5
REFIN(+)
Positive Reference Input. REFIN(+) can lie anywhere between VDD and GND + 0.1 V. The nominal reference
voltage (REFIN(+) REFIN()) is 2.5 V, but the part functions with a reference from 0.1 V to VDD.
6
REFIN()
Negative Reference Input. This reference input can lie anywhere between GND and VDD 0.1 V.
7
GND
Ground Reference Point.
8
VDD
Supply Voltage. 3 V or 5 V nominal.
9
DOUT/RDY
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word
information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY
pin is three-stated, but the RDY bit remains active.
10
DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers within the ADC; the register selection bits of the communications register identify the appropriate
register.
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