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參數(shù)資料
| 型號(hào)： | AD7776AR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 1CH HS 24-SOIC T/R |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 37.8k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
AD7776/AD7777/AD7778
–3–
REV. A
TIMING SPECIFICATIONS1, 2(V
CC = +5 V
5%; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
t
3
t
11
t
10
t
9
t
8
FIRST
CONVERSION
FINISHED
(CR6 = 0)
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
t
9
BUSY
(CR8 = 0)
INT
(CR8 = 1)
t
10
WR, RD
Figure 3.
BUSY/INT Timing
IOL
1.6mA
+2.1V
IOH
200
A
COUT
100pF
DB n
Figure 4. Load Circuit for Bus Timing Characteristics
t1
CS
t2
t4
t5
RD
DB0–DB9
Figure 1. Read Cycle Timing
t1
CS
t2
t6
WR
DB0–DB9
t3
t7
Figure 2. Write Cycle Timing
Parameter
Label
Limit at TMIN to TMAX Unit
Test Conditions/Comments
INTERFACE TIMING
CS Falling Edge to WR or RD Falling Edge
t1
0
ns min
WR or RD Rising Edge to CS Rising Edge
t2
0
ns min
WR Pulsewidth
t3
53
ns min
CS or RD Active to Valid Data3, 4
t4
60
ns max
Timed from Whichever Occurs Last
Bus Relinquish Time after
RD3, 5
t5
10
ns min
45
ns max
Data Valid to
WR Rising Edge
t6
55
ns min
Data Valid after
WR Rising Edge
t7
10
ns min
WR Rising Edge to BUSY Falling Edge
t8
1.5 tCLKIN
ns min
CR9 = 0
2.5 tCLKIN + 70
ns max
WR Rising Edge to BUSY Rising Edge or
INT Falling Edge
t9
19.5 tCLKIN + 70
ns max
Single Conversion, CR6 = 0
t10
33.5 tCLKIN + 70
ns max
Double Conversion, CR6 = 1
WR or RD Falling Edge to INT Rising Edge
t11
60
ns max
CR9 = 1
NOTES
1See Figures 1 to 3.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3100% production tested. All other times are guaranteed by design, not production tested.
4t
4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5t
5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t 5 quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
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