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參數(shù)資料
| 型號： | AD776 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 100 kSPS Oversampling ADC(16位100kSPS過采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 16位100 kSPS的采樣ADC的（16位100ksps的過采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 257K |
| 代理商： | AD776 |
AD776
–6–
REV. A
T he resulting output data stream is presented in a format
equivalent to a traditional ADC at a much reduced output
sample rate.
SIGNAL
SPECTRUM
FREQUENCY BAND
OF INTEREST
QUANTIZATION
NOISE
A
fC
fS
FREQUENCY
Figure 1. Noise Spectrum from Oversampling
SIGNAL
SPECTRUM
FREQUENCY BAND
OF INTEREST
SHAPED
QUANTIZATION
NOISE
A
fC
fS
FREQUENCY
TRANSFER FUNCTION OF
DIGITAL LOW-PASS FILTER
Figure 2. Noise Shaping
Figure 3 provides a block diagram of the various sections of the
AD776. T he Analog Front End is comprised of three differen-
tial switched capacitor linear integrators which perform the
noise-shaping function. Digital filter complexity of the AD776
is reduced by performing the filtering and decimation in two
stages. T he first section contains a 16:1 decimating comb filter
stage with the output presented to a 4:1 decimating low-pass/
compensation FIR filter, resulting in a final decimation ratio of
64:1. T he decimation function is described in detail in the
DECIMAT ION paragraph. T he output data is presented in
twos complement, MSB first serial data format, providing serial
communication to a host processor.
T his interface uses three dedicated pins: serial data output
(DOUT ), frame sync output (FSO), and serial clock output
(DOUT CLK ). T he serial interface format of operation is pin
selectable. T he timing diagrams for the serial interface are
described in the
DIGIT AL T IMING
section.
ANALOG
FRONT
END
16:1
DECIMATION
COMB
FILTER
SYSTEM TIMING AND CONTROL
4:1
DECIMATION
FIR
FILTER
SERIAL
INTERFACE
AD776
5
4
1
13
9
11
10
AGND
CLKIN
FSI
SF
DOE
DOUT
CLK
20
2
3
AIN+
AIN–
REFIN
19
REFOUT
8
6
FSEL
DV
DD
18
AV
DD
DGND
DOUT
6.4MHz
12.8MHz
3.2MHz
6.4MHz
7
12
FSO
X
U
M
V
REF
Figure 3. Block Diagram
ANALOG FRONT E ND
T he integrators of the third-order modulator front end form
a differential switched-capacitor network which results in
increased signal swing, increased power supply rejection, and
reduced sensitivity to clock jitter. Due to the nature of switched-
capacitor circuits, the input impedance of AIN+, AIN–, and
REFIN will vary with clock frequency. More information about
these inputs is given in T able II and T able III.
T he AD776 modulator is a third-order noise shaper which re-
duces quantization noise in the passband to the 16-bit level.
T he input signal is sampled at the rate of CLK IN/4. Since the
input signal is oversampled by a factor of 64, a complex anti-
aliasing filter is not needed; a single-pole RC filter will generally
be sufficient. High quality polystyrene or NPO ceramic capaci-
tors should be used for this filter.
DIGIT AL FILT E R OVE RVIE W
T he digital filters of the AD776 have two functions: high perfor-
mance low-pass filtering and digital decimation. T he shaped
quantization noise from the output of the modulator is low-pass
filtered to reduce the out-of-band noise components to a level
which will not alias into the passband during the decimation
process. Decimation then reduces the data rate to a manageable
level.
DE C IMAT ION
T he comb filter performs the first-stage filtering of the analog
front-end’s quantized and noise-shaped output and decimates
the input sample rate by a factor of 16:1. T he z-domain transfer
function for the comb filter is expressed by
H
(
z
)
=
(1±
z
±16
)
(1±
z
±1
)
4
4
T he frequency domain equivalent transfer function is
H
(
f
)
=
1
16
sin
(16
π
fT
)
sin
(
π
fT
)
4
where
T
=
1/
f
S
f
S
= the input sample rate for the Analog Front End
f
S
=
(maximum 6.4 MHz).
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