參數(shù)資料
型號(hào)： AD7739BRU-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/32頁(yè)
文件大小： 0K
描述： IC ADC 24BIT 8CH SIG-DEL 24TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 15.1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
配用： EVAL-AD7739EBZ-ND - BOARD EVAL FOR AD7739
AD7739
Data Sheet
Rev. A | Page 28 of 32
VOLTAGE REFERENCE INPUTS
The AD7739 has a differential reference input, REF IN(+) and
REF IN(). The common-mode range for these inputs is from
AGND to AVDD. The nominal differential reference voltage for
specified operation is 2.5 V. Both reference inputs feature dynamic
load. Therefore, connect the reference inputs to a low impedance
reference voltage source. External resistance/capacitance
combinations may result in gain errors on the part.
The output noise performance outlined in Table 5 through
Table 10 is for an analog input of 0 V and is unaffected by noise
on the reference. Obtaining the same noise performance as
shown in the noise tables over the full input range requires a
low noise reference source for the AD7739. If the reference
noise in the bandwidth of interest is excessive, it degrades the
performance of the AD7739.
Recommended reference voltage sources for the AD7739
REFERENCE DETECT
The AD7739 includes on-chip circuitry to detect if the part has
a valid reference for conversions. If the voltage between the
REFIN(+) and REFIN() pins goes below the NOREF trigger
voltage (0.5 V typ.) and the AD7739 is performing a conversion,
the NOREF bit in the channel status register is set.
I/O PORT
The AD7739 P0 pin can be used as a general-purpose digital
output or as a common analog input.
The P1 pin (SYNC/P1) can be used as a general-purpose digital
I/O pin or to synchronize the AD7739 with other devices in the
system. When the sync bit in the I/O port register is set and
the SYNC pin is low, the AD7739 does not process any
conversion. If it is put into single conversion mode, continuous
conversion mode, or any calibration mode, the AD7739 waits
until the SYNC pin goes high and then starts operation. This
allows conversion to start from a known point in time, that is,
the rising edge of the SYNC pin. When configured as input,
the SYNC pin must be tied high or low.
The digital P0 and P1 voltage is referenced to the analog
supplies.
CALIBRATION
The AD7739 provides zero-scale self-calibration, and zero- and
full-scale system calibration capability that can effectively
reduce the offset error and gain error to the order of the noise.
After each conversion, the ADC conversion result is scaled
using the ADC calibration registers and the relevant channel
calibration registers before being written to the data register.
For unipolar ranges,
Data = ((ADC Result R × ADC ZS Calibration Register) ×
ADC FS Register/(0x20 0000) R ×
Channel ZS Calibration Register) ×
Channel FS Calibration Register/(0x20 0000)
For bipolar ranges,
Data = ((ADC Result R × ADC ZS Calibration Register) ×
ADC FS Register/(0x40 0000) + (0x80 0000) R ×
Channel ZS Calibration Register) ×
Channel FS Calibration Register/(0x20 0000)
where:
The ADC Result is in the range of 0 to 0xFF FFFF.
R = 1 for input ranges +1.25 V, ±1.25 V, +2.5 V, and ±2.5 V, and
R = 2 for input ranges +0.625 V, and ±0.625 V.
Note that the channel zero-scale calibration register has the
format of a sign bit and a 22-bit channel offset value.
To start any calibration, write the relevant mode bits to the
AD7739 mode register. After the calibration is complete, the
contents of the corresponding calibration registers are updated,
all RDY bits in the ADC status register are set, the SYNC pin
goes low, and the AD7739 reverts to idle mode. The calibration
duration is the same as the conversion time configured on the
selected channel. A longer conversion time gives less noise and
yields a more exact calibration; therefore, use at least the default
conversion time to initiate any calibration.
ADC Zero-Scale Self-Calibration
The ADC zero-scale self-calibration can reduce the ADC offset
error in the chopping disabled mode. If repeated after a
temperature change, it can also reduce the offset drift error in
the chopping disabled mode.
The zero-scale self-calibration is performed on internally shorted
ADC inputs. The negative analog input terminal on the selected
channel is used to set the ADC zero-scale calibration common
mode. Therefore, either the negative terminal of the selected
differential pair or the AINCOM on the single-ended channel
configuration must be driven to a proper common-mode voltage.
It is recommended that the ADC zero-scale calibration register
be updated only as part of an ADC zero-scale self-calibration.
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