參數(shù)資料
型號(hào)： AD7738BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 8-CH 28-TSSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 779 (CN2011-ZH PDF)
配用： EVAL-AD7738EBZ-ND - BOARD EVAL FOR AD7738
REV. 0
AD7738
–13–
REGISTER DESCRIPTION
The AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are
specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communication
register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register
will be subsequently read or written.
Communications Register
8 Bits, Write-Only Register, Address 00h
All communications to the part must start with a write operation to the Communications register. The data written to the Commu-
nications register determines whether the subsequent operation will be a read or write and to which register this operation will be
directly placed. The digital interface defaults to expect write operation to the Communication register after power on, after reset, or
after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset
by writing at least 32 serial clock cycles with DIN high and
CS low (Note that all of the parts including modulator, filter, interface
and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or
with the DUMP bit and “24/16” bit in the Mode register set.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
0
R/
W
6-Bit Register Address
Bit
Mnemonic
Description
70
This bit must be zero for proper operation.
6R/
W
A zero in this bit indicates that the next operation will be a write to a specified register.
A one in this bit indicates that the next operation will be a read from a specified register.
5–0
Address
Address specifying to which register the read or write operation will be directed.
For channel specific registers the three LSBs, i.e., Bit 2, Bit 1, and Bit 0, specify the channel number.
When the subsequent operation writes to the Mode register, then the three LSBs specify the channel
selected for operation determined by the Mode register value. See Table X.
(The analog input’s configuration depends on the COM1, COM0 bits in the Channel Setup register.)
Table X.
Bit 2
Bit 1
Bit 0
Channel
Single Input
Differential Input
000
0
AIN0
AIN0–AIN1
001
1
AIN1
AIN2–AIN3
010
2
AIN2
AIN4–AIN5
011
3
AIN3
AIN6–AIN7
100
4
AIN4
AIN0–AIN1
101
5
AIN5
AIN2–AIN3
110
6
AIN6
AIN4–AIN5
111
7
AIN7
AIN6–AIN7
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