參數(shù)資料
型號(hào)： AD7738BRU
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 8-Channel, High Throughput,
中文描述： 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： MO-153AE, TSSOP-28
文件頁(yè)數(shù)： 22/28頁(yè)
文件大?。?/td> 407K
代理商： AD7738BRU
REV. 0
–22–
AD7738
Continuous Conversion Mode
When the Mode register is being written, the ADC Status Byte
is cleared and the
RDY
pin goes high regardless of its previous
state. When the continuous conversion command is written to
the Mode register, the ADC starts conversion on the channel
selected by the address of the Mode register.
After the conversion is complete, the relevant Channel Data
register and Channel Status register are updated, the
relevant
RDY bit in the ADC Status register is set, and the AD7738
continues converting on the next enabled channel. The
AD7738 will cycle through all enabled channels until put
into
another mode or reset. The cycle period will be the sum of
all enabled channels’ conversion times, set by corresponding
Channel Conversion Time registers.
The RDY bit is reset when the relevant Channel Data register
is
being read. The behavior of the
RDY
pin depends on the
RDYFN bit in the I/O Port register. When RDYFN bit is 0, the
RDY
pin goes low when any channel has unread data. When
this bit is set to 1 the
RDY
pin will only go low if all enabled
channels have unread data.
If an ADC conversion result has not been read before a new
ADC conversion is completed, then the new result will overwrite
the previous one. The relevant RDY bit goes low and the
RDY
pin goes high for at least 163 MCLK cycles (~26.5
μ
s), indicating
when the Data register is updated and the previous conversion
data is lost.
If the Data register is being read as an ADC conversion completes,
then the Data Register will not be updated with the new result (to
avoid data corruption) and the new conversion data is lost.
Figure 9 shows the digital interface signals sequence for the
Continuous Conversion mode with Channels 0 and 1 enabled
and the RDYFN bit set to 0. The
RDY
pin goes low and the
Data Register is read after each conversion. Figure 10 shows a
similar sequence, but with the RDYFN bit set to 1. The
RDY
pin goes low and the Data register is read after all conversions
are completed. Figure 11 shows the
RDY
pin when no data are
read from the AD7738.
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
START
CONTINUOUS
CONVERSION
SERIAL
INTERFACE
READ
DATA
CH0
READ
DATA
CH1
READ
DATA
CH0
READ
DATA
CH1
RDY
Figure 9. Continuous Conversion, CH0 and CH1, RDYFN = 0
RDY
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
READ
DATA
CH0
READ
DATA
CH1
START
CONTINUOUS
CONVERSION
SERIAL
INTERFACE
READ
DATA
CH0
READ
DATA
CH1
Figure 10. Continuous Conversion, CH0 and CH1, RDYFN = 1
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
Figure 11. Continuous Conversion, CH0 and CH1, No Data Read
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