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參數(shù)資料
| 型號： | AD7734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, +-10 V Input Range, High Throughput, 24-Bit sigma ∆ ADC |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 1542K |
| 代理商： | AD7734 |
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AD7734
TIMING SPECIFICATIONS
Table 2. (AV
DD
= 5 V ± 5%; DV
DD
= 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DV
DD
;
unless otherwise noted.)
1
Parameter
Min
Typ
Max
Master Clock Range
1
6.144
t
1
50
t
2
500
Read Operation
t
4
0
t
52
0
60
0
80
t
5A2, 3
0
60
0
80
t
6
50
t
7
50
t
8
0
t
94
10
80
Write Operation
t
11
0
t
12
30
t
13
25
t
14
50
t
15
50
t
16
0
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
SYNC Pulsewidth
RESET Pulsewidth
CS Falling Edge to SCLK Falling Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
CS Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
CS Falling Edge to SCLK Falling Edge Setup
Data Valid to SCLK Rising Edge Setup Time
Data Valid after SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of
1.6 V. See Figure 2 and Figure 3.
2
These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
3
4
This specification is relevant only if CS goes low while SCLK is low.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Rev. 0 | Page 6 of 32
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| AD7734BRU | 功能描述:IC ADC 24BIT 4-CH 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7734BRU-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 3.05Msps 24-bit Serial 28-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 15.437KSPS 24BIT SERL 28TSSOP - Tape and Reel |
| AD7734BRU-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 3.05Msps 24-bit Serial 28-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 15.437KSPS 24BIT SERL 28TSSOP - Tape and Reel |
| AD7734BRUZ | 功能描述:IC ADC 24BIT 4-CH 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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