參數資料
型號： AD7731BRZ-REEL7
廠商： Analog Devices Inc
文件頁數： 32/44頁
文件大小： 0K
描述： IC ADC 24BIT SIGMA-DELTA 24-SOIC
標準包裝： 400
位數： 24
采樣率（每秒）： 6.4k
數據接口： DSP，串行，SPI?
轉換器數目： 1
功率耗散（最大）： 125mW
電壓電源： 模擬和數字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數目和類型： 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極
配用： EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731
AD7731
–38–
REV. 0
The 8XC51 is configured in its Mode 0 serial interface mode.
Its serial interface contains a single data line. As a result, the
DATA OUT and DATA IN pins of the AD7731 should be
connected together. This means that the AD7731 must not be
configured for continuous read operation when interfacing to
the 8XC51. The serial clock on the 8XC51 idles high between
data transfers and, therefore, the POL input of the AD7731
should be hard-wired to a logic high. The 8XC51 outputs the
LSB first in a write operation while the AD7731 expects the
MSB first so the data to be transmitted has to be rearranged
before being written to the output serial register. Similarly, the
AD7731 outputs the MSB first during a read operation while
the 8XC51 expects the LSB first. Therefore, the data read into
the serial buffer needs to be rearranged before the correct data
word from the AD7731 is available in the accumulator.
SYNC
RESET
AD7731
POL
DATA OUT
DATA IN
SCLK
CS
P3.0
P3.1
8XC51
DVDD
Figure 19. AD7731 to 8XC51 Interface
AD7731 to ADSP-2103/ADSP-2105 Interface
Figure 20 shows an interface between the AD7731 and the
ADSP-2105 DSP processor. In the interface shown, the
RDY
bit of the Status Register is again monitored to determine when
the Data Register is updated. The alternative scheme is to use
an interrupt driven system, in which case the
RDY output is
connected to the
IRQ2 input of the ADSP-2105. The RFS and
TFS pins of the ADSP-2105 are configured as active low out-
puts and the ADSP-2105 serial clock line, SCLK, is also config-
ured as an output. The POL pin of the AD7731 is hard-wired
low. Because the SCLK from the ADSP-2105 is a continuous
clock, the
CS of the AD7731 must be used to gate off the clock
once the transfer is complete. The
CS for the AD7731 is active
when either the
RFS or TFS outputs from the ADSP-2105 are
active. The serial clock rate on the ADSP-2105 should be lim-
ited to 3 MHz to ensure correct operation with the AD7731.
SYNC
RESET
AD7731
DATA OUT
DATA IN
SCLK
CS
DR
SCLK
ADSP-2105
DVDD
RFS
TFS
DT
POL
Figure 20. AD7731 to ADSP-2105 Interface
REV. A
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相關代理商/技術參數
參數描述
AD7731EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise High Throughput 24-Bit Sigma-Delta ADC(411.99 k)
AD7732 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel, +-10 V Input Range, High Throughput, 24-Bit SIGMA- ADC
AD7732BRU 功能描述:IC ADC 24BIT 2-CH 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極
AD7732BRU-REEL 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 15.437ksps 24-bit Serial 28-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 15.437KSPS 24BIT SERL 28TSSOP - Tape and Reel
AD7732BRU-REEL7 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 15.437ksps 24-bit Serial 28-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 15.437KSPS 24BIT SERL 28TSSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:2 DIFF CH :10V INPUT, 28-BIT SD ADC - Tape and Reel
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