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參數(shù)資料
| 型號： | AD7731BR-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.4k |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–34–
REV. 0
SERIAL INTERFACE
The AD7731’s programmable functions are controlled via a set
of on-chip registers. Access to these registers is via the part’s
serial interface. After power-on or RESET, the device expects a
write to its Communications Register. The data written to this
register determines whether the next operation to the part is a
read or a write operation and also determines to which register
this read or write operation occurs. Therefore, write access to
one of the control registers on the part starts with a write opera-
tion to the Communications Register followed by a write to the
selected register. Reading from the part’s on-chip registers can
either take the form of a single read or continuous read. A single
read from a register consists of a write to the Communications
Register (with RW1 = 0 and RW0 = 1) followed by the read
from the specified register. To perform continuous reads from a
register, write to the Communications Register (with RW1 = 1
and RW0 = 0) to place the part in continuous read mode. The
specified register can then be read from continuously until a
write operation to the Communications Register (with RW1 = 1
and RW0 = 1) which takes the part out of continuous read
mode. When operating in continuous read mode, the part is
continuously monitoring its DIN line. Therefore, the DIN line
should be permanently low to allow the part to stay in continu-
ous read mode. Figure 5 and Figure 6, shown previously, indi-
cate the correct flow diagrams when reading and writing from
the AD7731’s registers.
The AD7731’s serial interface consists of five signals,
CS, SCLK,
DIN, DOUT and
RDY. The DIN line is used for transferring
data into the on-chip registers while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on DIN
or DOUT) take place with respect to this SCLK signal.
Write Operation
The transfer of data into the part is to an input shift register. On
completion of a write operation, data is transferred to the speci-
fied register. This internal transfer will not take place until the
correct number of bits for the specified register have been
loaded to the input shift register. For example, the transfer of
data from the input shift register takes place after eight serial
clock cycles for a DAC Register write while the transfer of data
from the input shift register takes place after 24 serial clock
cycles when writing to the Filter Register. Figure 16 shows a
timing diagram for a write operation to the input shift register of
the AD7731. With the POL input at a logic high, the data is
latched into the input shift register on the rising edge of SCLK.
With the POL input at a logic low, the data is latched into the
input shift register on the falling edge of SCLK.
Figure 16 also shows the
CS input being used to decode the
write operation to the AD7731. However, this
CS input can be
used in a number of different ways. It is possible to operate the
part in three-wire mode where the
CS input is permanently tied
low. In this case, the SCLK line should idle high between data
transfer when the POL input is high and should idle low be-
tween data transfers when the POL input is low. For POL = 1,
the first falling edge of SCLK clocks data from the microcontroller
onto the DIN line of the AD7731. It is then clocked into the
input shift register on the next rising edge of SCLK. For POL = 0,
the first clock edge which clocks data from the microcontroller
onto the DIN line of the AD7731 is a rising edge. It is then
clocked into the input shift register on the next falling edge of
SCLK.
In other microcontroller applications, which require a decoding
of the AD7731,
CS can be generated from a port line. In this
case,
CS would go low well in advance of the first falling edge of
SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).
Clocking of each bit of data is as just described.
In DSP applications, the SCLK is generally a continuous clock.
In these applications, the
CS input for the AD7731 is generated
from a frame synchronization signal from the DSP. For proces-
sors with the rising edge of SCLK as the active edge, the POL
input should be tied high. For processors with the falling edge of
SCLK as the active edge, the POL input should be tied low. In
these applications, the first edge after
CS goes low is the active
edge. The MSB of the data to be shifted into the AD7731 must
be set up prior to this first active edge.
DIN
SCLK
(POL = 1)
CS
MSB
t12
t15
LSB
t16
t14
t11
t13
SCLK
(POL = 0)
t14
t15
Figure 16. Write Cycle Timing Diagram
REV. A
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