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參數(shù)資料
| 型號： | AD7721ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SIGMA-DELTA 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 468.75k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
AD7721
REV. A
–4–
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(A, S Versions)
Units
Conditions/Comments
Serial Interface
fCLK
3
100
kHz min
Master Clock Frequency
15
MHz max
15 MHz for Specified Performance
tCLK LO
0.45
× t
CLK
ns min
Master Clock Input Low Time
tCLK HI
0.45
× t
CLK
ns min
Master Clock Input High Time
t1
tCLK
ns nom
DRDY High Time
t2
4
tCLK HI – 10
ns min
RFS Low to SCLK Falling Edge Setup Time
t3
20
ns max
RFS Low to Data Valid Delay
t4
tCLK HI
ns nom
SCLK High Pulse Width
t5
tCLK LO
ns nom
SCLK Low Pulse Width
t6
25
ns max
SCLK Rising Edge to Data Valid Delay
t7
0
ns min
RFS to SCLK Falling Edge Hold Time
t8
5
0
ns min
Bus Relinquish Time after Rising Edge of
RFS
20
ns max
t9
32
× t
CLK
ns nom
Period between Consecutive
DRDY Rising Edges
Parallel Interface
fCLK
3
100
kHz min
Master Clock Frequency
10
MHz max
10 MHz for Specified Performance
tCLK LO
0.45
× t
CLK
ns min
Master Clock Input Low Time
tCLK HI
0.45
× t
CLK
ns min
Master Clock Input High Time
Read Operation
t10
2
× t
CLK
ns nom
DRDY High Time
t11
30
ns max
Data Access Time after Falling Edge of
DRDY
t12
32
× t
CLK
ns nom
Period between Consecutive
DRDY Rising Edges
Write Operation
t13
35
ns min
WR Pulse Width
t14
20
ns min
Data Valid to
WR High Setup Time
t15
0
ns min
Data Valid to
WR High Hold Time
NOTES
The timing is measured with a load of 50 pF on SCLK and
DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2All digital outputs are timed with the load circuit below and, except for t
2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
3The AD7721 is production tested with f
CLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.
4t
2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V.
5t
8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
TO
OUTPUT
PIN
+1.6V
IOH
IOL
CL
50pF
1.6mA
200 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(AVDD= +5 V
5%; DVDD= +5 V
5%; AGND = DGND = 0 V, REFIN = +2.5 V
unless otherwise noted)
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| AD7721ARZ-REEL | 功能描述:IC ADC 16BIT SIGMA-DELTA 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7721SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7722 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| AD7722AS | 制造商:Rochester Electronics LLC 功能描述:16-BIT SIGMA-DELTA CONVERTER I.C. - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7722AS-ES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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