Y Versions1 Units Conditions/Comments STATIC PERFORMANCE No Missing Codes 24 Bits min Guarant" />
參數(shù)資料
型號： AD7714YRZ
廠商： Analog Devices Inc
文件頁數(shù)： 36/40頁
文件大?。?/td> 0K
描述： IC ADC 24BIT SIGMA-DELTA 24SOIC
標準包裝： 31
位數(shù)： 24
采樣率（每秒）： 1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極
配用： EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714
Parameter
Y Versions1
Units
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
24
Bits min
Guaranteed by Design. For Filter Notches
≤ 60 Hz
22
Bits min
For Filter Notch = 100 Hz
18
Bits min
For Filter Notch = 250 Hz
15
Bits min
For Filter Notch = 500 Hz
12
Bits min
For Filter Notch = 1 kHz
Output Noise
See Tables I to IV
Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity
±0.001
% of FSR max
Filter Notches
≤ 60 Hz.
Unipolar Offset Error
See Note 2
Unipolar Offset Drift3
0.4
V/°C typ
For Gains of 1, 2, 4
0.1
V/°C typ
For Gains of 8, 16, 32, 64, 128
Bipolar Zero Error
See Note 2
Bipolar Zero Drift3
0.4
V/°C typ
For Gains of 1, 2, 4
0.1
V/°C typ
For Gains of 8, 16, 32, 64, 128
Positive Full-Scale Error4
See Note 2
Full-Scale Drift3, 5
0.4
V/°C typ
For Gains of 1, 2, 4
0.1
V/°C typ
For Gains of 8, 16, 32, 64, 128
Gain Error6
See Note 2
Gain Drift3, 7
0.2
ppm of FSR/
°C typ
Bipolar Negative Full-Scale Error2
±0.0015
% of FSR max
AVDD = 5 V. Typically
±0.0004%
±0.003
% of FSR max
AVDD = 3 V. Typically
±0.0004%
Bipolar Negative Full-Scale Drift3
1
V/°C typ
For Gains of 1 to 4
0.6
V/°C typ
For Gains of 8 to 128
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR)8
90
dB min
At DC. Typically 102 dB.
Normal-Mode 50 Hz Rejection8
100
dB min
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection8
100
dB min
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±0.02 × f
NOTCH
Common-Mode 50 Hz Rejection8
150
dB min
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±0.02 × f
NOTCH
Common-Mode 60 Hz Rejection8
150
dB min
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±0.02 × f
NOTCH
Absolute/Common-Mode REF IN Voltage8
AGND to AVDD
V min to V max
Absolute/Common-Mode AIN Voltage8, 9
AGND – 30 mV
V min
BUF Bit of Setup Register = 0
AVDD + 30 mV
V max
Absolute/Common-Mode AIN Voltage8, 9
AGND + 50 mV
V min
BUF Bit of Setup Register = 1
AVDD – 1.5 V
V max
AIN DC Input Current8
1
nA max
AIN Sampling Capacitance8
7
pF max
AIN Differential Voltage Range10
0 to +VREF/GAIN
11
nom
Unipolar Input Range (B/U Bit of Filter High Register = 1)
±V
REF/GAIN
nom
Bipolar Input Range (B/U Bit of Filter High Register = 0)
AIN Input Sampling Rate, fS
GAIN
× f
CLK IN/64
For Gains of 1 to 4
fCLK IN/8
For Gains of 8 to 128
Reference Input Range
REF IN(+) – REF IN(–) Voltage
1/1.75
V min/max
AVDD = 2.7 V to 3.3 V. VREF = 1.25 ± 1% for Specified Performance
REF IN(+) – REF IN(–) Voltage
1/3.5
V min/max
AVDD = 4.75 V to 5.25 V. VREF = 2.5 ± 1% for Specified Performance
REF IN Input Sampling Rate, fS
fCLK IN/64
LOGIC INPUTS
Input Current
±10
A max
All Inputs Except MCLK IN
VINL, Input Low Voltage
0.8
V max
DVDD = 5 V
0.4
V max
DVDD = 3 V
VINH, Input High Voltage
2.4
V min
DVDD = 5 V
2
V min
DVDD = 3 V
SCLK & DIN Only (Schmitt Triggered Input)
DVDD = 5 V NOMINAL
VT+
1.4/3
V min/V max
VT–
0.8/1.4
V min/V max
VT+ – VT–
0.4/0.8
V min/V max
SCLK & DIN Only (Schmitt Triggered Input)
DVDD = 3 V NOMINAL
VT+
1/2.5
V min/V max
VT–
0.4/1.1
V min/V max
VT+ – VT–
0.375/0.8
V min/V max
MCLK In Only
DVDD = 5 V NOMINAL
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
3.5
V min
MCLK In Only
DVDD = 3 V NOMINAL
VINL, Input Low Voltage
0.4
V max
VINH, Input High Voltage
2.5
V min
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
0.4
V max
ISINK = 800 A with DVDD = 5 V. Except for MCLK OUT
12
VOL, Output Low Voltage
0.4
V max
ISINK = 100 A with DVDD = 3 V. Except for MCLK OUT
12
VOH, Output High Voltage
4
V min
ISOURCE = 200 A with DVDD = 5 V. Except for MCLK OUT
12
AD7714Y–SPECIFICATIONS (AV
DD = DVDD = +2.7 V to +3.3 V or 4.75 V to 5.25 V, REF IN(+) = +1.25 V; with AVDD = 3 V
and +2.5 V with AVDD = 5 V; REF IN(–) = AGND; MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7714
REV. C
–5–
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參數(shù)描述
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