AVDD Temperature Package Model Supply Range Option* AD7714AN-5 5 V –" />
參數(shù)資料
型號(hào)： AD7714ARZ-3
廠商： Analog Devices Inc
文件頁數(shù)： 38/40頁
文件大?。?/td> 0K
描述： IC ADC 24BIT SIGMA-DELTA 24SOIC
標(biāo)準(zhǔn)包裝： 31
位數(shù)： 24
采樣率（每秒）： 1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極
配用： EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714
2
AD7714
REV. C
–7–
ORDERING GUIDE
AVDD
Temperature
Package
Model
Supply
Range
Option*
AD7714AN-5
5 V
–40
°C to +85°C
N-24
AD7714AR-5
5 V
–40
°C to +85°C
R-24
AD7714ARS-5
5 V
–40
°C to +85°C
RS-28
AD7714AN-3
3 V
–40
°C to +85°C
N-24
AD7714AR-3
3 V
–40
°C to +85°C
R-24
AD7714ARS-3
3 V
–40
°C to +85°C
RS-28
AD7714YN
3 V/5 V
–40
°C to +105°C
N-24
AD7714YR
3 V/5 V
–40
°C to +105°C
R-24
AD7714YRU
3 V/5 V
–40
°C to +105°C
RU-24
AD7714AChips-5
5 V
–40
°C to +85°CDie
AD7714AChips-3
3 V
–40
°C to +85°CDie
EVAL-AD7714-5EB 5 V
Evaluation Board
EVAL-AD7714-3EB 3 V
Evaluation Board
*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.
TIMING CHARACTERISTICS1, 2
(AVDD = DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLKIN = 2.5 MHz; Input Logic 0 = 0 V,
Logic 1 = DVDD unless otherwise noted.)
Limit at TMIN, TMAX
Parameter
(A, Y Versions)
Units
Conditions/Comments
fCLKIN
3, 4
400
kHz min
Master Clock Frequency: Crystal/Resonator or Externally
Supplied
2.5
MHz max
For Specified Performance
tCLK IN LO
0.4
× t
CLK IN
ns min
Master Clock Input Low Time. tCLK IN = 1/fCLK IN
tCLK IN HI
0.4
× t
CLK IN
ns min
Master Clock Input High Time
tDRDY
500
× t
CLK IN
ns nom
DRDY High Time
t1
100
ns min
SYNC Pulsewidth
t2
100
ns min
RESET Pulsewidth
Read Operation
t3
0
ns min
DRDY to CS Setup Time
t4
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time5
t5
6
0
ns min
SCLK Active Edge to Data Valid Delay5
80
ns max
DVDD = +5 V
100
ns max
DVDD = +3 V
t6
100
ns min
SCLK High Pulsewidth
t7
100
ns min
SCLK Low Pulsewidth
t8
0
ns min
CS Rising Edge to SCLK Active Edge Hold Time5
t9
7
10
ns min
Bus Relinquish Time after SCLK Active Edge5
60
ns max
DVDD = +5 V
100
ns max
DVDD = +3 V
t10
100
ns max
SCLK Active Edge to
DRDY High5, 8
Write Operation
t11
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time5
t12
30
ns min
Data Valid to SCLK Edge Setup Time
t13
20
ns min
Data Valid to SCLK Edge Hold Time
t14
100
ns min
SCLK High Pulsewidth
t15
100
ns min
SCLK Low Pulsewidth
t16
0
ns min
CS Rising Edge to SCLK Edge Hold Time
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD) and timed from a voltage level of 1.6 V.
2See Figures 6 and 7. Timing applies for all grades.
3CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4The AD7714 is production tested with f
CLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.
5SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL or VOH limits.
7These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
8
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
TO OUTPUT
PIN
50pF
ISINK (800 A AT DVDD = +5V
100 A AT DVDD = +3.3V)
+1.6V
ISOURCE (200 A AT DVDD = +5V
100 A AT DVDD = +3.3V)
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AD7714ARZ-3REEL 功能描述:IC ADC 24BIT SIGMA-DELTA 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
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