參數(shù)資料
型號(hào)： AD7711AR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Signal Conditioning ADC with RTD Excitation Currents
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： MS-013AD, SOIC-24
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 242K
代理商： AD7711AR
REV. F
–6–
AD7711
Limit at T
MIN
, T
MAX
(A, S Versions)
Parameter
Units
Conditions/Comments
External Clocking Mode
f
SCLK
t
20
t
21
t
22
t
t
23
t
257
f
CLK IN
/5
0
0
2
×
t
CLK IN
0
4
×
t
CLK IN
10
2
×
t
CLK IN
+ 20
2
×
t
CLK IN
2
×
t
CLK IN
t
CLK IN
+ 10
10
t
CLK IN
+ 10
10
5
×
t
CLK IN
/2 + 50
0
0
4
×
t
CLK IN
2
×
t
CLK IN
– SCLK High
30
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Serial Clock Input Frequency
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
Data Access Time (
RFS
Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
t
26
t
27
t
t
28
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Falling Edge to
DRDY
High
SCLK to Data Valid Hold Time
t
t
30
t
32
t
33
t
34
t
35
t
36
RFS
/
TFS
to SCLK Falling Edge Hold Time
RFS
to Data Valid Hold Time
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
SCLK Falling Edge to
TFS
Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
The AD7711 is specified with a 10 MHz clock for AV
DD
voltages of +5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5
The AD7711 is production tested with f
CLK IN
at 10 MHz (8 MHz for AV
DD
> +5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
7
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
8
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
TO OUTPUT
PIN
100pF
200
m
A
1.6mA
+2.1V
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time
PIN CONFIGURATION
DIP AND SOIC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7711
AV
DD
V
SS
RTD2
RTD1
AIN1(–)
SCLK
MCLK IN
MCLK OUT
A0
AIN1(+)
MODE
SYNC
V
BIAS
REF IN(–)
REF IN(+)
REF OUT
AIN2
DGND
DV
DD
SDATA
DRDY
AGND
TFS
RFS
相關(guān)PDF資料
PDF描述
AD7711SQ LC2MOS Signal Conditioning ADC with RTD Excitation Currents
AD7711* LC2MOS Signal Conditioning ADC with RTD Excitation Currents
AD7711A Signal Conditioning ADC with RTD Current Source(帶RTD電流源信號(hào)調(diào)節(jié)A/D轉(zhuǎn)換器)
AD7711 LC2MOS Signal Conditioning ADC with RTD Excitation Currents(RTD激勵(lì)電流LC2MOS信號(hào)調(diào)節(jié)A/D轉(zhuǎn)換器)
AD7714(中文) Signal Conditioning ADC(信號(hào)調(diào)節(jié)A/D轉(zhuǎn)換器)
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