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參數(shù)資料
| 型號： | AD7710ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT DIFF INP 24-SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極 |
| 產品目錄頁面： | 778 (CN2011-ZH PDF) |
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AD7710
REV. G
–23–
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY line and does not have any effect on the status of
DRDY. A write operation to the control register or the calibra-
tion register must always write 24 bits.
Figure 13a shows a write operation to the AD7710 with
TFS
remaining low for the duration of the operation. A0 determines
whether a write operation transfers data to the control register
or to the calibration registers. This A0 signal must remain valid
for the duration of the serial write operation. As before, the
serial clock line should be low between read and write opera-
tions. The serial data to be loaded to the AD7710 must be valid
on the high level of the externally applied SCLK signal. Data is
clocked into the AD7710 on the high level of this SCLK signal
with the MSB transferred first. On the last active high time of
SCLK, the LSB is loaded to the AD7710.
Figure 13b shows a timing diagram for a write operation to the
AD7710 with
TFS returning high during the operation and
returning low again to write the rest of the data-word. Timing
parameters and functions are very similar to those outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when
TFS returns high in the middle
of transferring a word.
Data to be loaded to the AD7710 must be valid prior to the
rising edge of the SCLK signal.
TFS should return high during
the low time of SCLK. After
TFS returns low again, the next bit
of the data-word to be loaded to the AD7710 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7710.
t35
t33
SCLK (I)
SDATA (I)
A0 (I)
t32
MSB
LSB
t26
t27
t34
TFS (I)
t36
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
t35
SCLK (I)
SDATA (I)
TFS (I)
A0 (I)
MSB
BIT N
BIT N+1
t32
t26
t30
t27
t36
t35
t36
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation
(
TFS Returns High during Write Operation)
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參數(shù)描述 |
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| AD7710ARZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 1.02KSPS SOIC-24 |
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| AD7710SQ/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 24-Bit |
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