參數(shù)資料
型號(hào)： AD7710AR
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： Signal Conditioning ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： MS-013AD, SOIC-24
文件頁(yè)數(shù)： 12/28頁(yè)
文件大小： 220K
代理商： AD7710AR
REV. F
–12–
AD7710
1k
10
0.1
10
1k
10k
100
1
100
NOTCH FREQUENCY – Hz
O
m
V
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
Figure 2b. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7710 in the external clocking mode with
both the AV
DD
and DV
DD
pins of the AD7710 being driven
from the analog +5 V supply. Some applications will have
separate supplies for both AV
DD
and DV
DD
, and in some of
these cases, the analog supply will exceed the +5 V digital sup-
ply (see Power Supplies and Grounding section).
REF IN(+)
V
BIAS
REF OUT
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
AGND
V
SS
DGND
MCLK IN
MCLK OUT
MODE
SCLK
SDATA
DRDY
TFS
RFS
REF IN(–)
SYNC
A0
DIFFERENTIAL
ANALOG INPUT
ANALOG
GROUND
DIGITAL
GROUND
DATA
READY
TRANSMIT
(WRITE)
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
ADDRESS
INPUT
+5V
AD7710
10
m
F
0.1
m
F
0.1
m
F
ANALOG
+5V SUPPLY
AV
DD
DV
DD
I
OUT
DIFFERENTIAL
ANALOG INPUT
Figure 3. Basic Connection Diagram
Figure 2 gives similar information to that outlined in Table I. In this plot, the output rms noise is shown for the full range of avail-
able cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots are
typical values at 25
°
C.
10k
100
0.1
10
1k
10k
1k
10
1
100
NOTCH FREQUENCY – Hz
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
O
m
V
Figure 2a. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
CIRCUIT DESCRIPTION
The AD7710 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in weigh scale, industrial
control or process control applications. It contains a sigma-delta
(or charge balancing) ADC, a calibration microcontroller with
on-chip static RAM, a clock oscillator, a digital filter and a bi-
directional serial communications port.
The part contains two programmable gain differential analog
input channels. The gain range is from 1 to 128 allowing the
part to accept unipolar signals of between 0 mV to +20 mV and
0 V to +2.5 V or bipolar signals in the range from
±
20 mV to
±
2.5 V when the reference input voltage equals +2.5 V. The
input signal to the selected analog input channel is continuously
sampled at a rate determined by the frequency of the master
clock, MCLK IN, and the selected gain (see Table III). A
charge-balancing A/D converter (Sigma-Delta Modulator) con-
verts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma-
delta modulator with the input sampling frequency being modi-
fied to give the higher gains. A sinc
3
digital low-pass filter
processes the output of the sigma-delta modulator and updates
the output register at a rate determined by the first notch fre-
quency of this filter. The output data can be read from the serial
port randomly or periodically at any rate up to the output regis-
ter update rate. The first notch of this digital filter (and hence its
–3 dB frequency) can be programmed via an on-chip control
register. The programmable range for this first notch frequency
is from 9.76 Hz to 1.028 kHz, giving a programmable range for
the –3 dB frequency of 2.58 Hz to 269 Hz.
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