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參數(shù)資料
| 型號： | AD7710 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Signal Conditioning ADC(LC2MOS信號調(diào)節(jié)A/D轉(zhuǎn)換器) |
| 中文描述： | 信號調(diào)理模數(shù)轉(zhuǎn)換器（LC2MOS信號調(diào)節(jié)的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 236K |
| 代理商： | AD7710 |
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AD7710
REV. E
–17–
USING THE AD7710
SYSTEM DESIGN CONSIDERATIONS
The AD7710 operates differently from successive approxima-
tion ADCs or integrating ADCs. Since it samples the signal
continuously, like a tracking ADC, there is no need for a start
convert command. The output register is updated at a rate
determined by the first notch of the filter and the output can be
read at any time, either synchronously or asynchronously.
Clocking
The AD7710 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be con-
nected between MCLK IN and MCLK OUT, in which case the
clock circuit will function as a crystal controlled oscillator. For
lower clock frequencies, a ceramic resonator may be used
instead of the crystal. For these lower frequency oscillators,
external capacitors may be required on either the ceramic reso-
nator or on the crystal.
The input sampling frequency, the modulator sampling fre-
quency, the –3 dB frequency, output update rate and calibration
time are all directly related to the master clock frequency,
f
CLK IN
. Reducing the master clock frequency by a factor of two
will halve the above frequencies and update rate and will double
the calibration time.
The current drawn from the DV
DD
power supply is also directly
related to f
CLK IN
. Reducing f
CLK IN
by a factor of two will halve
the DV
DD
current but will not affect the current drawn from the
AV
DD
power supply.
System Synchronization
If multiple AD7710s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the
SYNC
input resets the filter and
places the AD7710 into a consistent, known state. A common
signal to the AD7710s’
SYNC
inputs will synchronize their
operation. This would normally be done after each AD7710 has
performed its own calibration or has had calibration coefficients
loaded to it.
The
SYNC
input can also be used to reset the digital filter in
systems where the turn-on time of the digital power supply
(DV
DD
) is very long. In such cases, the AD7710 will start oper-
ating internally before the DV
DD
line has reached its minimum
operating level, +4.75 V. With a low DV
DD
voltage, the
AD7710’s internal digital filter logic does not operate correctly.
Thus, the AD7710 may have clocked itself into an incorrect
operating condition by the time that DV
DD
has reached its cor-
rect level. The digital filter will be reset upon issue of a calibra-
tion command (whether it is self-calibration, system calibration
or background calibration) to the AD7710. This ensures correct
operation of the AD7710. In systems where the power-on
default conditions of the AD7710 are acceptable, and no cali-
bration is performed after power-on, issuing a
SYNC
pulse to
the AD7710 will reset the AD7710’s digital filter logic. An R, C
on the
SYNC
line, with R, C time constant longer than the
DV
DD
power-on time, will perform the
SYNC
function.
ACCURACY
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance. The AD7710 achieves excellent
linearity by the use of high quality, on-chip silicon dioxide
capacitors, which have a very low capacitance/voltage coeffi-
cient. The device also achieves low input drift through the use
of chopper stabilized techniques in its input stage. To ensure
excellent performance over time and temperature, the AD7710
uses digital calibration techniques which minimize offset and
gain error.
AUTOCALIBRATION
Autocalibration on the AD7710 removes offset and gain errors
from the device. A calibration routine should be initiated on the
device whenever there is a change in the ambient operating
temperature or supply voltage. It should also be initiated if there
is a change in the selected gain, filter notch or bipolar/unipolar
input range. However, if the AD7710 is in its background cali-
bration mode, the above changes are all automatically taken care
of (after the settling time of the filter has been allowed for).
The AD7710 offers self-calibration, system calibration and
background calibration facilities. For calibration to occur on the
selected channel, the on-chip microcontroller must record the
modulator output for two different input conditions. These are
“zero-scale” and “full-scale” points. With these readings, the
microcontroller can calculate the gain slope for the input to
output transfer function of the converter. Internally, the part
works with a resolution of 33 bits to determine its conversion
result of either 16 bits or 24 bits.
The AD7710 also provides the facility to write to the on-chip
calibration registers and in this manner the span and offset for
the part can be adjusted by the user. The offset calibration regis-
ter contains a value which is subtracted from all conversion
results, while the full-scale calibration register contains a value
which is multiplied by all conversion results. The offset calibra-
tion coefficient is subtracted from the result prior to the multi-
plication by the full-scale coefficient. In the first three modes
outlined here, the
DRDY
line indicates that calibration is com-
plete by going low. If
DRDY
is low before (or goes low during)
the calibration command, it may take up to one modulator cycle
before
DRDY
goes high to indicate that calibration is in
progress. Therefore,
DRDY
should be ignored for up to one
modulator cycle after the last bit of the calibration command is
written to the control register.
Self-Calibration
In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (i.e., AIN(+) = AIN(–) = V
BIAS
) and
the full-scale point is V
REF
. The zero-scale coefficient is deter-
mined by converting an internal shorted inputs node. The full-
scale coefficient is determined from the span between this
shorted inputs conversion and a conversion on an internal V
REF
node. The self-calibration mode is invoked by writing the appro-
priate values (0, 0, 1) to the MD2, MD1 and MD0 bits of the
control register. In this calibration mode, the shorted inputs
node is switched in to the modulator first and a conversion is
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