TIMING CHARACTERISTICS1, 2 Limit at TMIN
參數(shù)資料
型號: AD7709BRU-REEL
廠商: Analog Devices Inc
文件頁數(shù): 29/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT SIGMA-DELTA 24TSSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 105
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 3.75mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極;2 個差分,雙極;4 個偽差分,單極;4 個偽差分,雙極
REV. A
AD7709
–6–
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(A, B Version)
Unit
Conditions/Comments
t1
30.5176
ms typ
Crystal Oscillator Period
t2
50
ns min
RESET Pulsewidth
Read Operation
t3
0
ns min
RDY to CS Setup Time
t4
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time3
t5
4
0
ns min
SCLK Active Edge to Data Valid Delay
3
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.7 V to 3.6 V
t5A
4, 5
0
ns min
CS Falling Edge to Data Valid Delay
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.7 V to 3.6 V
t6
100
ns min
SCLK High Pulsewidth
t7
100
ns min
SCLK Low Pulsewidth
t8
0
ns min
CS Rising Edge to SCLK Inactive Edge Hold Time3
t9
6
10
ns min
Bus Relinquish Time after SCLK Inactive Edge
3
80
ns max
t10
100
ns max
SCLK Active Edge to
RDY High3, 7
Write Operation
t11
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time3
t12
30
ns min
Data Valid to SCLK Edge Setup Time
t13
25
ns min
Data Valid to SCLK Edge Hold Time
t14
100
ns min
SCLK High Pulsewidth
t15
100
ns min
SCLK Low Pulsewidth
t16
0
ns min
CS Rising Edge to SCLK Edge Hold Time
NOTES
1 Sample tested during initial release to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figures 2 and 3.
3 SCLK active edge is falling edge of SCLK.
4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL or VOH limits.
5 This specification comes into play only if
CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish
times of the part and as such are independent of external bus loading capacitances.
7
RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.
(VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = VDD unless otherwise noted.)
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