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參數(shù)資料
型號(hào): AD7680ARM
廠商: Analog Devices Inc
文件頁(yè)數(shù): 23/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT LP 100KSPS 8-MSOP
標(biāo)準(zhǔn)包裝: 50
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 100k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 26.4mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,單極
AD7680
Rev. A | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03643-0-003
CS
SDATA
SCLK
6
5
4
VDD 1
GND
2
VIN 3
AD7680
TOP VIEW
(Not to Scale)
SOT-23
Figure 3. SOT-23 Pin Configuration
03643-0-022
NC = NO CONNECT
AD7680
MSOP
TOP VIEW
(Not to Scale)
VDD 1
GND
2
GND
3
VIN 4
CS
SDATA
NC
SCLK
8
7
6
5
Figure 4. MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
SOT-23
Pin No.
MSOP
Mnemonic
Function
1
VDD
Power Supply Input. The VDD range for the AD7680 is from 2.5 V to 5.5 V.
2
2, 3
GND
Analog Ground. Ground reference point for all circuitry on the AD7680. All analog input signals should
be referred to this GND voltage.
3
4
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
4
5
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock
input is also used as the clock source for the AD7680's conversion process.
5
7
SDATA
Data Out. Logic output. The conversion result from the AD7680 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7680 consists of four leading zeros followed by 16 bits of conversion data that are provided MSB
first. This will be followed by four trailing zeroes if CS is held low for a total of 24 SCLK cycles. See the
section.
6
8
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7680 and framing the serial data transfer.
N/A
6
NC
No Connect. This pin should be left unconnected.
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