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參數(shù)資料
| 型號： | AD7679ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT SAR W/BUFF 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 570k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 103mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7679CBZ-ND - BOARD EVALUATION FOR AD7679 |
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AD7679
Rev. A | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
MODE0
MODE1
D0/OB/2C
NC
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
BUSY
D17
D16
D15
AD7679
D5/DIVSCLK[1]
D14
P
DBU
F
AV
D
RE
F
BUF
IN
NC
AG
ND
IN
+
NC
IN
–
RE
F
G
ND
RE
F
D6/
E
X
T
/I
NT
D
7
/IN
V
S
Y
N
C
D
8
/I
N
VSC
L
K
D9/
RDC/
S
D
IN
OGN
D
OV
D
DV
D
DG
ND
D10/
S
D
O
U
T
D1
1
/SC
L
K
D12/
S
Y
NC
D13/
RDE
RR
O
R
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION
IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES HOWEVER,
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF THE SYSTEM.
03
08
5-
0
04
Figure 4.
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 44
AGND
P
Analog Power Ground Pin.
2, 47
AVDD
P
Input Analog Power Pins. Nominally 5 V.
3
MODE0
DI
Data Output Interface Mode Selection.
4
MODE1
DI
Data Output Interface Mode Selection:
Interface MODE
MODE1
MODE0
Description
0
18-Bit Interface
1
0
1
16-Bit Interface
2
1
0
Byte Interface
3
1
Serial Interface
5
D0/OB/2C
DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is
inverted, resulting in a twos complement output from its internal shift register.
6, 7, 40–
42, 45
NC
No Connect.
8
D1/A0
DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all
other modes, this input pin controls the form in which data is output, as shown in Table 7.
9
D2/A1
DI/O
When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output
bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
10
D3
DO
In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin
is always an output, regardless of the interface mode.
11, 12
D[4:5]or
DIVSCLK[0:1]
DI/O
In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock
that clocks the data output. In other serial modes, these pins are not used.
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