參數(shù)資料
型號(hào)： AD7666ACPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT UNIPOLAR 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 75mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)偽差分，單極
配用： EVAL-AD7666CBZ-ND - BOARD EVALUATION FOR AD7666
AD7666
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7666 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7666 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
While the AD7666 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7666 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
X15
X14
X
1
2
3
14
151617
18
t34
03033-0-034
EXT/INT = 1
RD
RD = 0
Figure 41. Slave Serial Data Timing for Reading (Read after Convert)
SDOUT
SCLK
D1
D0
X
D15
D14
D13
12
3
14
15
16
t3
t35
t36 t37
t31
t32
t16
BUSY
EXT/INT = 1
INVSCLK = 0
03033-0-035
CNVST
CS
RD = 0
Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7666AST 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:500KSPS, 16-BIT ACD INT. REF, 2.5LSB - Tape and Reel 制造商:Analog Devices 功能描述:16BIT ADC INT REF 7666 LQFP48
AD7666ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP T/R
AD7666ASTZ 功能描述:IC ADC 16BIT UNIPOLAR 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6
AD7666ASTZRL 功能描述:IC ADC 16BIT UNIPOLAR 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD7667 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref
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