參數資料
型號: AD7653ASTZRL
廠商: Analog Devices Inc
文件頁數: 14/28頁
文件大?。?/td> 0K
描述: IC ADC 16BIT UNIPOLAR 48LQFP
標準包裝: 2,000
系列: PulSAR®
位數: 16
采樣率(每秒): 1M
數據接口: 串行,并聯(lián)
轉換器數目: 1
功率耗散(最大): 145mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數目和類型: 2 個偽差分,單極
配用: EVAL-AD7653CBZ-ND - BOARD EVALUATION FOR AD7653
AD7653
Usually, because the AD7653 is used with a fast throughput, the
Master Read During Conversion mode is the most
recommended serial mode. In this mode, the serial clock and
data toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
MASTER SERIAL INTERFACE
Internal Clock
The AD7653 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held LOW. The
AD7653 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. F
and
show
the detailed timing diagrams of these two modes.
Figure 32. Master Serial Data Timing for Reading (Read after Convert)
Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
t3
BUSY
SYNC
SCLK
SDOUT
t28
t29
t14
t18
t19
t20
t21
t24
t26
t27
t23
t22
t16
t15
12
3
14
15
16
D15
D14
D2
D1
D0
X
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t25
t30
02966-0-015
CNVST
CS, RD
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t3
t1
t17
t14
t19
t20 t21
t24
t26
t25
t27
t23
t22
t16
t15
D15
D14
D2
D1
D0
X
12
3
14
15
16
t18
BUSY
SYNC
SCLK
SDOUT
02966-0-016
CNVST
CS, RD
Rev. A | Page 21 of 28
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