參數(shù)資料
型號(hào)： AD7641BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT 2MSPS SAR 48-LQFP
產(chǎn)品培訓(xùn)模塊： ADC Applications
ADC Architectures
ADC DC/AC Performance
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 18
采樣率（每秒）： 2M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 92mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
配用： EVAL-AD7641CBZ-ND - BOARD EVALUATION FOR AD7641
AD7641
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
MODE0
MODE1
D0/OB/2C
NC = NO CONNECT
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
BUSY
D17
D16
D15
AD7641
D5/DIVSCLK[1]
D14
D
6/
E
X
T
/IN
T
D
7/
IN
VSYN
C
D8/
IN
V
S
CL
K
D9/
RDC/
S
D
IN
OG
N
D
OV
D
DV
DD
DG
ND
D10/
S
D
O
U
T
D1
1/
SC
LK
D12
/S
Y
NC
D13
/RDE
RRO
R
P
DBUF
P
DRE
F
RE
F
BUF
IN
TE
M
P
AV
D
IN
+
AG
ND
AG
ND
NC
IN
–
RE
F
G
ND
RE
F
WARP
04
76
1-
0
04
NORMAL
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
Mnemonic
Type1
Description
1, 36,
41, 42
AGND
P
Analog Power Ground Pin.
2, 44
AVDD
P
Input Analog Power Pins. Nominally 2.5 V.
3, 4
MODE[0:1]
DI
Data Output Interface Mode Selection.
Interface MODE#
MODE1
MODE0
Description
0
18-bit interface
1
0
1
16-bit interface
2
1
0
8-bit (byte) interface
3
1
Serial interface
5
D0/OB/2C
DI/O
When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus
and the data coding is straight binary. In all other modes, this pin allows the choice of straight
binary/twos complement. When OB/2C is high, the digital output is straight binary; when low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
6
WARP
DI
Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp
mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and
a minimum conversion rate must be applied to guarantee full specified accuracy.
7
NORMAL
DI
Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode
where full accuracy is maintained independent of the minimum conversion rate.
8
D1/A0
DI/O
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Table 7.
9
D2/A1
DI/O
When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
10
D3
D0
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
11, 12
D[4:5]
DI/O
When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
or DIVSCLK[0:1]
When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read
after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the
internally generated serial clock that clocks the data output. In other serial modes, these pins are
high impedance outputs.
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