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參數(shù)資料
| 型號： | AD7626BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 10MSPS DIFF 32LFCSP |
| 設(shè)計(jì)資源： | Single-Ended-to-Differential High Speed Drive Circuit for 16-Bit, 10 MSPS AD7626 ADC (CN0105) |
| 特色產(chǎn)品： | AD7626 PulSAR Differential ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 170mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，雙極 |
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AD7626
Data Sheet
Rev. B | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
07
648-
0
02
NOTES
1. CONNECT THE EXPOSED PAD TO THE GROUND
PLANE OF THE PCB USING MULTIPLE VIAS.
VDD1
VDD2
CAP1
REFIN
EN0
EN1
VDD2
CNV–
GND
IN+
IN–
VCM
VDD1
VDD2
CLK+
C
N
V
+
D
–
D
+
V
IO
G
N
D
C
O
–
D
C
O
+
C
L
K
–
R
E
F
G
N
D
R
E
F
R
E
F
C
A
P
2
G
N
D
C
A
P
2
C
A
P
2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD7626
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
VDD1
P
Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor.
2
VDD2
P
Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should
supply this pin first, then be traced to the other VDD2 pins (Pin 7 and Pin 18).
3
CAP1
AO
Connect this pin to a 10 nF capacitor.
4
REFIN
AI/O
Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage
and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280.
In either internal or external reference mode, a 10 μF capacitor is required. If using an external 4.096 V
reference (connected to REF), this pin is a no connect and does not require any capacitor.
5, 6
EN0, EN1
DI
Enable. Operates from 2.5 V logic. The logic levels of these pins set the operation of the device as
follows:
EN1 = 0, EN0 = 0: power-down mode.
EN1 = 0, EN0 = 1: external 1.2 V reference applied to the REFIN pin required.
EN1 = 1, EN0 = 0: external 4.096 V reference applied to the REF pin required.
EN1 = 1, EN0 = 1: internal reference and internal reference buffer in use.
7
VDD2
P
Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
8, 9
CNV, CNV+
DI
Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the
analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when
CNV is grounded; otherwise, CNV+ and CNV are differential LVDS inputs.
10, 11
D, D+
DO
LVDS Data Outputs. The conversion data is output serially on these pins.
12
VIO
P
Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor.
13
GND
P
Ground. Return path for the 100 nF capacitor connected to Pin 12.
14, 15
DCO, DCO+
DO
LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected.
In this mode, the 16-bit results on D are preceded by an initial 0 (which is output at the end of the
previous conversion), followed by a 2-bit header (10) to allow synchronization of the data by the
digital host with extra logic. The 1 in this header provides the reference to acquire the subsequent
conversion result correctly. When DCO+ is not grounded, the echoed-clock interface mode is
selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+
and can be captured in the digital host on the next rising edge of DCO+.
16, 17
CLK, CLK+
DI
LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+.
18
VDD2
P
Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
19, 20
VDD1
P
Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF
capacitor.
21
VCM
AO
Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage
present on the REF pin, which can be useful for driving the common mode of the input amplifiers.
22
IN
AI
Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+.
23
IN+
AI
Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN.
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| AD7626BCPZ-RL7 | 功能描述:IC ADC 16BIT 10MSPS DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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| AD7628BFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
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| AD7628BQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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