參數(shù)資料
型號: AD7606BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 27/36頁
文件大小: 0K
描述: IC DAS W/ADC 16BIT 8CH 64LQFP
設(shè)計資源: Layout Considerations for an Expandable Multichannel Simultaneous Sampling Data Acquisition System Based on AD7606 (CN0148)
標(biāo)準(zhǔn)包裝: 1
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 16 b
采樣率(每秒): 200k
數(shù)據(jù)接口: DSP,MICROWIRE?,并聯(lián),QSPI?,串行,SPI?
電壓電源: 模擬和數(shù)字
電源電壓: 2.3 V ~ 5.25 V,4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
Data Sheet
AD7606/AD7606-6/AD7606-4
Rev. C | Page 33 of 36
To ensure good device-to-device performance matching in
a system that contains multiple AD7606/AD7606-6/AD7606-4
devices, a symmetrical layout between the AD7606/AD7606-6/
AD7606-4 devices is important.
Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4
devices. The AVCC supply plane runs to the right of both devices,
and the VDRIVE supply track runs to the left of the two devices.
The reference chip is positioned between the two devices, and
the reference voltage track runs north to Pin 42 of U1 and south
to Pin 42 of U2. A solid ground plane is used.
These symmetrical layout principles can also be applied to a system
that contains more than two AD7606/AD7606-6/AD7606-4
devices. The AD7606/AD7606-6/AD7606-4 devices can be placed
in a north-south direction, with the reference voltage located
midway between the devices and the reference track running in
the north-south direction, similar to Figure 64.
AVCC
U2
U1
AVCC
U2
U1
08479-
056
Figure 64. Layout for Multiple AD7606 Devices—Top Layer and
Supply Plane Layer
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