參數資料
| 型號： | AD7568BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 9/14頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT OCTAL LC2MOS 44MQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 500ns |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 17.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸出數目和類型： | 16 電流，單極；16 電流，雙極 |
| 采樣率（每秒）： | 2M |
| 產品目錄頁面： | 785 (CN2011-ZH PDF) |
AD7568
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Parameter
Rating
VDD to DGND
0.3 V to +6 V
IOUT1 to DGND
0.3 V to VDD +0.3 V
IOUT2 to DGND
0.3 V to VDD +0.3 V
Digital Input Voltage to DGND
0.3 V to VDD +0.3 V
VRFB, VREF to DGND
±15 V
Operating Temperature Range
Commercial Plastic (B Versions)
40°C to +85°C
Storage Temperature Range
65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Power Dissipation (Any Package) to 75°C
250 mW
Derates above 75°C by
10 mW/°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 Transient currents of up to 100 mA will not cause SCR latch-up.
PIN DESCRIPTION
Mnemonic
Description
VDD
Positive Power Supply. This is 5 V ± 5%.
DGND
Digital Ground.
AGND
Analog Ground
VREFA to VREFH
DAC Reference Inputs.
RFBA to RFBH
DAC Feedback Resistor Pins.
IOUTA to IOUTH
DAC Current Output Terminals.
AGND
This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
CLKIN
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.
FSIN
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it
enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low.
SDIN
Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally
comes the three DAC select bits. These determine which DAC in the device is selected for loading.
SDOUT
This shift register output allows multiple devices to be connected in a daisy-chain configuration.
A0
Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the
data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
LDAC
Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the
input latches.
CLR
Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.
– 4 –
REV. C
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