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參數(shù)資料
| 型號： | AD7521LN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 12BIT 1MHZ 2LSB 18-DIP |
| 標準包裝： | 20 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 20mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 18-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1M |
2
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . . -100mV to V+
Operating Conditions
Temperature Ranges
JN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
θJC (oC/W)
16 Ld PDIP Package
90
N/A
18 Ld PDIP Package
80
N/A
Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in
conductive foam at all times.
Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK.
1.
θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
AD7520
AD7521
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
SYSTEM PERFORMANCE (Note 2)
Resolution
10
12
Bits
Nonlinearity
J
-10V
≤ VREF ≤ +10V
--
±0.2
(8-Bit)
--
-
% of
FSR
L
-10V
≤ VREF ≤ +10V
(Figure 2)
--
±0.05
(10-Bit)
--
±0.05
(10-Bit)
% of
FSR
Nonlinearity Tempco
-10V
≤ VREF ≤ +10V
(Notes 3, 4)
--
±2-
-
±2
ppm of
FSR/oC
Gain Error
-
±0.3
-
±0.3
-
% of
FSR
Gain Error Tempco
-
±10
-
±10
ppm of
FSR/oC
Output Leakage Current
(Either Output)
Over the Specified
Temperature Range
--
±200
-
±200
nA
DYNAMIC CHARACTERISTICS
Output Current Settling Time
To 0.05% of FSR (All Digital
Inputs Low To High And High
-1.0
-
1.0
-
s
Feedthrough Error
VREF = 20VP-P, 100kHz
All Digital Inputs Low (Note 4)
(Figure 6)
-
10
-
10
mVP-P
REFERENCE INPUT
Input Resistance
All Digital Inputs High
IOUT1 at Ground
5
10
20
5
10
20
k
ANALOG OUTPUT
Output Capacitance
IOUT1 All Digital Inputs High
-
200
-
200
-
pF
IOUT2
-
75-
-
75-
pF
IOUT1 All Digital Inputs Low
-
75-
-
75-
pF
IOUT2
-
200
-
200
-
pF
Output Noise
Both Outputs
-
to 10k
-
Equivalent
to 10k
-
Johnson
Noise
DIGITAL INPUTS
Low State Threshold, VIL
Over the Specified
Temperature Range
VIN = 0V or +15V
--
0.8
-
0.8
V
High State Threshold, VIH
2.4
-
2.4
-
V
Input Current, IIL, IIH
--
±1-
-
±1
A
Input Coding
Binary/Offset Binary
AD7520, AD7521
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