V
參數(shù)資料
型號(hào)： AD7490BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 16CH 1MSPS 28TSSOP
產(chǎn)品變化通告： IDD Specification Change 17/Jun/2009
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 16 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
Data Sheet
AD7490
Rev. D | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
02691-
003
AD7490
TOP VIEW
(Not to Scale)
VIN11 1
VIN12
28
VIN10 2
VIN13
27
VIN9 3
VIN14
26
NC
4
VIN15
25
VIN8 5
AGND
24
VIN7 6
REFIN
23
VIN6 7
VDD
22
VIN5 8
AGND
21
VIN4 9
CS
20
VIN3 10
DIN
19
VIN2 11
NC
18
VIN1 12
VDRIVE
17
VIN0 13
SCLK
16
AGND 14
DOUT
15
NC = NO CONNECT
ALL NC PINS SHOULD BE
CONNECTED STRAIGHT TO AGND
Figure 3. 28-Lead TSSOP Pin Configuration
02691-
032
NOTES
1. NC = NO CONNECT. ALL NC PINS
SHOULD BE CONNECTED STRAIGHT
TO AGND.
2. CONNECT EXPOSED PAD TO GND
AD7490
TOP VIEW
(Not to Scale)
1
VIN15
2
NC
3
AGND
4
REFIN
5
VDD
6
AGND
7
CS
8
DIN
24
23
22
21
20
19
18
17
NC
VIN8
VIN7
VIN6
VIN5
VIN4
VIN3
NC
9
10
11
12
13
14
15
16
V
IN
2
V
IN
1
V
IN
0
AG
ND
DO
UT
S
CL
K
V
DRI
V
E
NC
32
31
30
29
28
27
26
25
NC
V
IN
9
V
IN
10
V
IN
11
V
IN
12
V
IN
13
V
IN
14
NC
Figure 4. 32-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
TSSOP
LFCSP
20
18
CS
Chip Select. Active low logic input. This input provides the dual function of initiating
conversions on the AD7490 and also frames the serial data transfer.
23
21
REFIN
Reference Input for the AD7490. An external reference must be applied to this input. The
voltage range for the external reference is 2.5 V ± 1% for specified performance.
22
20
VDD
Power Supply Input. The VDD range for the AD7490 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN
range, VDD should be from 4.75 V to 5.25 V.
14, 21, 24
12, 19, 22
AGND
Analog Ground. Ground reference point for all circuitry on the AD7490. All analog/digital input
signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected together.
13 to 5,
3 to 1,
28 to 25
11 to 9,
7 to 2,
31 to 26,
24
VIN0 to VIN15
Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are
multiplexed into the on chip track-and-hold. The analog input channel to be converted is
selected by using the address bits ADD3 through ADD0 of the control register. The address bits,
in conjunction with the SEQ and SHADOW bits, allow the sequence register to be programmed.
The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected
via the RANGE bit in the control register. Any unused input channels should be connected to
AGND to avoid noise pickup.
19
17
DIN
Data In. Logic input. Data to be written to the control register of the AD7490 is provided on this
input and is clocked into the register on the falling edge of SCLK (see the Control Register
section).
15
13
DOUT
Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data
stream consists of four address bits indicating which channel the conversion result corresponds
to, followed by the 12 bits of conversion data, which is provided by MSB first. The output coding
can be selected as straight binary or twos complement via the CODING bit in the control
register.
16
14
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This
clock input is also used as the clock source for the conversion process of the AD7490.
17
15
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial
interface of the AD7490 operates.
N/A
EP
EPAD
Exposed Pad. Connect exposed pad to GND.
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