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參數(shù)資料
| 型號： | AD7484BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SAR 3MSPS 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 90mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7484CBZ-ND - BOARD EVALUATION FOR AD7484 |
AD7484
Rev. C | Page 13 of 20
For higher input bandwidth applications, the AD8021 op amp
(also available as a dual AD8022 op amp) is the recommended
choice to drive the AD7484. Figure 15 shows the analog input
circuit used to obtain the data for the FFT plot shown in Figure 4.
A bipolar analog signal is applied to the terminal and biased
up with a stable, low noise dc voltage connected, as shown in
Figure 12. A 10 pF compensation capacitor is connected between
Pin 5 of the AD8021 and the negative supply. The AD8021 is
supplied with +12 V and 12 V supplies. The supply pins are
decoupled as close to the device as possible, with both a 0.1 F
and a 10 F capacitor connected to each pin. In each case, the
0.1 F capacitor should be the closer of the two caps to the
device. The AD8021 logic reference pin is tied to analog ground,
and the DISABLE
ADC TRANSFER FUNCTION
pin is tied to the positive supply. Detailed
information on the AD8021 is available at www.analog.com.
The output coding of the AD7484 is straight binary. The designed
code transitions occur midway between the successive integer
LSB values, that is, 1/2 LSB, 3/2 LSB, and so on. The LSB size is
VREF/16,384. The nominal transfer characteristic for the AD7484 is
shown in Figure 16. This transfer characteristic may be shifted
as detailed in the Offset/Overrange section.
000...000
0V
ADC
CO
DE
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
0.5LSB
+VREF – 1.5LSB
1LSB = VREF/16384
02642-
016
Figure 16. AD7484 Transfer Characteristic
POWER SAVING
The AD7484 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition, the
AD7484 features two power saving modes, nap and standby.
These modes are selected by bringing either the NAP pin or the
STBY pin to a logic high, respectively.
When operating the AD7484 in normal fully powered mode,
the current consumption is 18 mA during conversion and the
quiescent current is 12 mA. Operating at a throughput rate of
1 MSPS, the conversion time of 300 ns contributes 27 mW to
the overall power dissipation.
(300 ns/1 μs) × (5 V × 18 mA) = 27 mW
For the remaining 700 ns of the cycle, the AD7484 dissipates
42 mW of power.
(700 ns/1 μs) × (5 V × 12 mA) = 42 mW
Therefore, the power dissipated during each cycle is
27 mW + 42 mW = 69 mW
Figure 17 shows the AD7484 conversion sequence operating in
normal mode.
CONVST
BUSY
300ns
1s
700ns
02642-
017
Figure 17. Normal Mode Power Dissipation
In nap mode, almost all of the internal circuitry is powered down.
In this mode, the power dissipation is reduced to 2.5 mW. When
using an external reference, there must be a minimum of 300 ns
from exiting nap mode to initiating a conversion. This is necessary
to allow the internal circuitry to settle after power-up and for
the track-and-hold to properly acquire the analog input signal.
The internal reference cannot be used in conjunction with the
nap mode.
If the AD7484 is put into nap mode after each conversion, the
average power dissipation is reduced, but the throughput rate is
limited by the power-up time. Using the AD7484 with a through-
put rate of 500 kSPS while placing the part in nap mode after
each conversion results in average power dissipation as follows:
The power-up phase contributes
(300 ns/2 μs) × (5 V × 12 mA) = 9 mW
The conversion phase contributes
(300 ns/2 μs) × (5 V × 18 mA) = 13.5 mW
While in nap mode for the rest of the cycle, the AD7484
dissipates only 1.75 mW of power.
(1400 ns/2 μs) × (5 V × 0.5 mA) = 1.75 mW
Therefore, the power dissipated during each cycle is
9 mW + 13.5 mW + 1.75 mW = 24.25 mW
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7484BSTZ | 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD7485 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1 MSPS, Serial 14-Bit SAR ADC |
| AD7485BST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 14-bit Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14 BIT, 1MSPS, SERIAL ADC I.C. - Tape and Reel 制造商:Analog Devices 功能描述:14BIT SERIAL ADC SMD 7485 LQFP48 |
| AD7485BSTZ | 功能描述:IC ADC 14BIT SAR 1MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7490 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
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