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參數(shù)資料
| 型號： | AD7401YRWZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR SIGMA-DELTA 16SOIC |
| 標準包裝： | 47 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 93.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
AD7401
Rev. D | Page 12 of 20
TERMINOLOGY
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
Integral Nonlinearity
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are specified negative
full-scale, 200 mV (VIN+ VIN), Code 12,288 for the 16-bit
level, and specified positive full-scale, +200 mV (VIN+ VIN),
Code 53,248 for the 16-bit level.
Offset Error
Offset error is the deviation of the midscale code (Code 32,768
for the 16-bit level) from the ideal VIN+ VIN (that is, 0 V).
Gain Error
Gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (53,248 for the
16-bit level) from the ideal VIN+ VIN (+200 mV) after the
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (12,288 for
the 16-bit level) from the ideal VIN+ VIN (200 mV) after the
offset error is adjusted out. Gain error includes reference error.
Signal-to-(Noise + Distortion) Ratio
This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Therefore, for a 12-bit converter, this is 74 dB.
Effective Number of Bits (ENOB)
The ENOB is defined by
ENOB = (SINAD 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7401, it is defined as
1
6
5
4
3
2
V
THD
2
log
20
)
dB
(
+
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±200 mV frequency, f, to the power of a 200 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN of
frequency fS, expressed as
CMRR (dB) = 10log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not converter linearity. PSRR is the maximum change in the
specified full-scale (±200 mV) transition point due to a change
in power supply voltage from the nominal value (see Figure 6).
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. (It was tested using a transient
pulse frequency of 100 kHz.)
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