參數(shù)資料
型號: AD7376ARWZ50
廠商: Analog Devices Inc
文件頁數(shù): 12/20頁
文件大?。?/td> 0K
描述: IC DIGITAL POT 50K 16-SOIC
標準包裝: 47
接片: 128
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標準值 300 ppm/°C
存儲器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 4.5 V ~ 33 V,±4.5 V ~ 16.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
產(chǎn)品目錄頁面: 787 (CN2011-ZH PDF)
配用: EVAL-AD7376EBZ-ND - BOARD EVAL FOR AD7376
AD7376
Rev. D | Page 2 of 20
TABLE OF CONTENTS
REVISION HISTORY
8/11—Rev. C to Rev. D
Changes to Output Logic Low Conditions, Table 1..................... 3
Changes to Output Logic Low Conditions, Table 2..................... 5
Changes to Figure 28...................................................................... 14
Updates Outline Dimensions........................................................ 18
7/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Updates Outline Dimensions........................................................ 19
Changes to Ordering Guide .......................................................... 20
3/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings....................................... 7
Changes to ESD Protection Section............................................. 14
Changes to Ordering Guide .......................................................... 19
11/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted DIP Package..........................................................Universal
Changes to Features ..........................................................................1
Separated Electrical Characteristics into Table 1 and Table 2.....3
Separated Interface Timing into Table 3 ........................................5
Changes to Table 1 Through Table 3...............................................3
Added Table 4 ....................................................................................6
Added Figure 2...................................................................................6
Changes to Absolute Maximum Ratings Section..........................7
Deleted Parametric Test Circuits Section.......................................7
Changes to Typical Performance Characteristics..........................9
Added Daisy-Chain Operation Section ...................................... 14
Added ESD Protection Section..................................................... 14
Added Terminal Voltage Operating Range Section................... 14
Added Power-Up and Power-Down Sequences Section........... 14
Added Layout and Power Supply Biasing Section ..................... 15
Added Applications Section.......................................................... 16
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 19
10/97—Revision 0: Initial Version
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