參數(shù)資料
型號(hào)： AD7367BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SAR 1MSPS 24TSSOP
設(shè)計(jì)資源： Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標(biāo)準(zhǔn)包裝： 62
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 88.8mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD7366/AD7367
Rev. D | Page 16 of 28
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7366/AD7367 are fast, dual, 2-channel, 12-/14-bit,
bipolar input, simultaneous sampling, serial ADCs. The
AD7366/AD7367 can accept bipolar input ranges of ±10 V
and ±5 V. They can also accept a unipolar input range of 0 V to
10 V. The AD7366/AD7367 require VDD and VSS dualsupplies
for the high voltage analog input structures. These supplies must
be equal to or greater than ±11.5 V. See Table 7 for the minimum
requirements on these supplies for each analog input range. The
AD7366/AD7367 require a low voltage 4.75 V to 5.25 V AVCC
supply to power the ADC core.
Table 7. Reference and Supply Requirements for Each
Analog Input Range
Selected
Analog Input
Range (V)
Reference
Voltage (V)
Full-Scale
Input
Range (V)
AVCC (V)
Minimum
VDD/VSS(V)
±10
2.5
±10
5
±11.5
3.0
±12
5
±12
±5
2.5
±5
5
±11.5
3.0
±6
5
±11.5
0 to 10
2.5
0 to 10
5
±11.5
3.0
0 to 12
5
±12
The AD7366/AD7367 contain two on-chip, track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. The AD7366/AD7367
are available in a 24-lead TSSOP, offering the user considerable
space-saving advantages over alternative solutions. The AD7366/
AD7367 require a CNVST signal to start conversion. On the
falling edge of CNVST, both track-and-holds are placed into
hold mode and the conversions are initiated. The BUSY signal
goes high to indicate that the conversions are taking place. The
clock source for each successive approximation ADC is provided
by an internal oscillator. The BUSY signal goes low to indicate
the end of conversion. On the falling edge of BUSY, the track-
and-hold returns to track mode. When the conversion is
finished, the serial clock input accesses data from the part.
The AD7366/AD7367 have an on-chip 2.5 V reference that can
be disabled if an external reference is preferred. If the internal
reference is to be used elsewhere in a system, the output from
DCAPA and DCAPB must first be buffered. On power-up, the
REFSEL pin must be tied to either a high or low logic state to
select either the internal or external reference option. If the
internal reference is the preferred option, the user must tie the
REFSEL pin logic high. Alternatively, if REFSEL is tied to GND
then an external reference can be supplied to both ADCs
through the DCAPA and DCAPB pins.
The analog inputs are configured as two single-ended inputs
for each ADC. The input voltage range can be selected by
programming the RANGE bits as shown in Table 8.
CONVERTER OPERATION
The AD7366/AD7367 have two successive approximation
ADCs, each based around two capacitive DACs. Figure 16 and
Figure 17 show simplified schematics of an ADC in acquisition
and conversion phases. The ADC comprises control logic, a
SAR, and a capacitive DAC. In Figure 16 (the acquisition phase),
SW2 is closed and SW1 is in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the signal on the input.
VIN
AGND
A
B
SW1
SW2
COMPARATOR
CAPACITIVE
DAC
CONTROL
LOGIC
06703-
018
Figure 16. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 17), SW2 opens
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is
balanced again, the conversion is complete. The control logic
generates the ADC output code.
VIN
AGND
A
B
SW1
SW2
COMPARATOR
CAPACITIVE
DAC
CONTROL
LOGIC
06703-
019
Figure 17. ADC Conversion Phase
ANALOG INPUTS
Each ADC in the AD7366/AD7367 has two single-ended
analog inputs. Figure 18 shows the equivalent circuit of the
analog input structure of the AD7366/AD7367. The two diodes
provide ESD protection. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. This causes these diodes to become forward-biased
and to start conducting current into the substrate. These diodes
can conduct up to 10 mA without causing irreversible damage
to the part. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors is
typically about 170 . Capacitor C1 can primarily be attributed
to pin capacitance, while Capacitor C2 is the sampling capacitor
of the ADC. The total lumped capacitance of C1 and C2 is
approximately 9 pF for the ±10 V input range and approxi-
mately 13 pF for all other input ranges.
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