參數(shù)資料
型號(hào)： AD73311LARUZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/36頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR FRONT END LP 20SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
通道數(shù)： 2
功率（瓦特）： 50mW
電壓 - 電源，模擬： 3V
電壓 - 電源，數(shù)字： 3V
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
AD73311
–28–
REV. B
APPENDIX A
Programming a Single AD73311 for Data Mode Operation
This section describes a typical sequence in programming a
single codec to operate in normal DATA mode. It details the
control (program) words that are sent to the device to configure
its internal registers and shows the typical output data received
during both program and data modes. The device is connected
in Frame Sync Loop-Back Mode (see Figure 13), which forces
an input word from the DSP’s Tx Reg each time the codec
outputs a word via the SDO/SDOFS lines. In Step 1, the part
has just been reset and on the first output event the codec pre-
sents an invalid output word
1. The DSP’s Tx Reg contains a
DSP TX REG
CONTROL WORD 1
1 0 000 001 00000011
ADC WORD 1 *
0000 0000 0000 0000
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 1
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 010 00000001
CONTROL WORD 1
1 0 000 001 00000011
ADC WORD 1 *
0000 0000 0000 0000
DSP RX REG
STEP 2
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 010 00000001
ADC WORD 1 *
1011 1001 0000 0011
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 3
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 000 00000001
CONTROL WORD 1
1 0 000 010 00000001
ADC WORD 1 *
1011 1001 0000 0011
DSP RX REG
STEP 4
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 000 00000001
ADC WORD 1 *
1011 1010 0000 0001
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 5
DSP TX REG
DEVICE 1
DAC WORD 1
0111 1111 1111 1111
CONTROL WORD 1
1 0 000 000 00000001
ADC WORD 1 *
1011 1010 0000 0001
DSP RX REG
STEP 6
DSP TX REG
DAC WORD 1
0111 1111 1111 1111
ADC WORD 1
1000 0000 0000 0000
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 7
DSP TX REG
DEVICE 1
DAC WORD 1
0111 1111 1111 1111
DAC WORD 1
0111 1111 1111 1111
ADC WORD 1
1000 0000 0000 0000
DSP RX REG
STEP 8
*ADC SAMPLES DURING PROGRAM MODE ARE INVALID.
DEVICE 1
Figure 33. Programming a Single AD73311 for Normal
control word that programs CRB with the data word 0x03. In
Step 2, the control word from the DSP’s Tx Reg has been sent
to the codec’s SPORT and the output word has been received
by the DSP’s Rx Reg. In Steps 3 and 4, register CRC is pro-
grammed with 0x01, which powers up the analog section. In
Steps 5 and 6, the codec is put into programming mode by
setting the
PGM/DATA bit of CRA. In Step 7, the output word
from the device is now a valid ADC word as the device has been
programmed into data mode. Note also that the codec now
expects DAC data to be sent to it and will interpret any data
from the DSP to be 16-bit DAC data.
NOTE
1Data output by the codec in program mode is invalid and should not be inter-
preted as ADC data. The only exception to this is output caused by register
reads or CEE being enabled on control word writes.
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