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參數(shù)資料
| 型號： | AD7324BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT+ SAR 4CHAN 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
| 配用： | EVAL-AD7324CBZ-ND - BOARD EVALUATION FOR AD7324CBZ |
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Data Sheet
AD7324
Rev. B | Page 31 of 36
SERIAL INTERFACE
Figure 51 shows the timing diagram for the serial interface of
the AD7324. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7324 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into hold
mode and takes the bus out of three-state. Then the analog input
signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14th SCLK
rising edge. On the 16th SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of CS occurs before 16 SCLK cycles
have elapsed, the conversion is terminated, and the DOUT line
returns to three-state. Depending on where the CS signal is brought
high, the addressed register may be updated.
Data is clocked into the AD7324 on the SCLK falling edge. The
3 MSBs on the DIN line are decoded to select which register is
being addressed. The control register is a 12-bit register. If the
control register is addressed by the 3 MSBs, the data on the DIN
line is loaded into the control on the 15th SCLK rising edge. If the
sequence register or the range register is addressed, the data on
the DIN line is loaded into the addressed register on the 11th SCLK
falling edge.
Conversion data is clocked out of the AD7324 on each SCLK
falling edge. Data on the DOUT line consists of a leading ZERO
bit, two channel identifier bits, a sign bit, and a 12-bit conversion
result. The channel identifier bits are used to indicate which
channel corresponds to the conversion result. The leading ZERO
bit is clocked out on the CS falling edge, and the first channel
identifier bit is clocked out on the first SCLK falling edge.
ADD1
1
2
3
4
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t2
t6
t4
t9
t10
t3
t7
t5
t8
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ZERO
2 IDENTIFICATION BITS
04864-
036
DON’T
CARE
Figure 51. Serial Interface Timing Diagram (Control Register Write)
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參數(shù)描述 |
|---|---|
| AD7327 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 kSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC |
| AD7327BRUZ | 功能描述:IC ADC 12BIT+ SAR 8CHAN 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7327BRUZ-REEL | 功能描述:IC ADC 12BIT+SAR 8CHAN 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7327BRUZ-REEL7 | 功能描述:IC ADC 12BIT+ SAR 8CHAN 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7328 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Channel, Software-Selectable True Bipolar Input, 12-Bit Plus Sign ADC |
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