參數(shù)資料
型號(hào)： AD7305YRZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 0K
描述： IC DAC 8BIT QUAD R-R 20SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 1µs
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 雙 ±
功率耗散（最大）： 60mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 1M
AD7304/AD7305
Rev. C | Page 16 of 20
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 =
LSB. Two address bits, A1 and A0, are decoded when an active
low write strobe is placed on the WR pin, see Table 6. The WR
is a level-sensitive input pin, therefore, the data setup and data
hold times defined in the Timing Specifications section need to
be adhered to.
AD7305
8
320k
280k
80k
640k
680k
VDD
LDAC
VSS
WR
VDD
VREF
GND
DATA
DB0–DB7
A1
A0/SHDN
R
POWER-
ON
RESET
DAC A
OE
DAC A
REGISTER
DAC B
OE
DAC B
REGISTER
DAC C
OE
DAC C
REGISTER
DAC D
OE
DAC D
REGISTER
DAC A
B
C
D
2:4
DECODE
VOUTC
VOUTB
VOUTA
VOUTD
01114-036
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
R
Figure 36. AD7305 Equivalent Logic Interface
The LDAC pin provides the capability of simultaneously
updating all DAC registers with new data from the input
registers at the same time. This results in the analog outputs all
changing to their new values at the same time. The LDAC pin is
a level-sensitive input. If the simultaneous update feature is not
required, the LDAC pin can be tied to logic low. When the
LDAC is tied to Logic Low, the DAC registers become
transparent and the input register data determines the DAC
output voltage (see Figure 36 for an equivalent interface logic
diagram).
AD7226 PIN COMPATIBILITY
By tying the LDAC pin to ground, the AD7305 has the same pin
configuration and functionality as the AD7226, with the
exception of a lower power supply operating voltage.
AD7305 HARDWARE SHUTDOWN SHDN
If a three-state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation,
no other termination voltages should be present on this pin. An
internal window comparator detects when the logic voltage on
the SHDN pin is between 28% and 36% of VDD. A high imped-
ance, internal-bias generator provides this voltage on the SHDN
pin. The four DAC output voltages become high impedance
with a nominal resistance of 120 k to ground.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The VREF pins also contain a back-
biased ESD protection Zener connected to VDD (see Figure 37).
GND
DIGITAL
INPUTS
VDD
VREFX
01114-037
Figure 37. Equivalent ESD Protection Circuits
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