參數(shù)資料
型號(hào): AD7305BRZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/20頁(yè)
文件大小: 0K
描述: IC DAC 8BIT QUAD 5V R-R 20-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 37
設(shè)置時(shí)間: 1µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 60mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 1M
產(chǎn)品目錄頁(yè)面: 784 (CN2011-ZH PDF)
AD7304/AD7305
Rev. C | Page 7 of 20
Table 6. AD7305 Control Logic Truth Table
WR 1
A1
A0
LDAC2
Input Register Function
DAC Register Function
L
H
Register A loaded with DB0 to DB7
Latched with previous contents, no change
↑+
L
H
Register A latched with DB0 to DB7
Latched with previous contents, no change
L
H
Register B loaded with DB0 to DB7
Latched with previous contents, no change
↑+
L
H
Register B latched with DB0 to DB7
Latched with previous contents, no change
L
H
L
H
Register C loaded with DB0 to DB7
Latched with previous contents, no change
↑+
H
L
H
Register C latched with DB0 to DB7
Latched with previous contents, no change
L
H
Register D loaded with DB0 to DB7
Latched with previous contents, no change
↑+
H
Register D latched with DB0 to DB7
Latched with previous contents, no change
H
X
L
No effect
All input register contents loaded, register transparent
L
X
L
Input register x transparent to DB0 to DB7
Register transparent
H
X
↑+
No effect
All input register contents latched
H
X
H
No effect, device not selected
1
↑+ positive logic transition; ↓– negative logic transition; X don’t care.
2
LDAC is a level-sensitive input.
tAH
tDH
tLH
tLDW
tWR
tAS
tDS
tLS
tS
±1 LSB
ERROR BAND
A0, A1
WR
D0–D7
LDAC
VOUT
01114-006
Figure 6. AD7305 General Timing Diagram
tSDR
A0/SHDN
IDD
tSDN
01114-007
Figure 7. AD7305 Timing Diagram Zoom In
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