TIMING CHARACTERISTICS1, 2 Limit at TMIN
參數(shù)資料
型號(hào): AD7302BRU
廠商: Analog Devices Inc
文件頁(yè)數(shù): 10/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 8BIT DUAL R-R 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 75
設(shè)置時(shí)間: 1.2µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 24.8mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): 833k
AD7302
–3–
REV. 0
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(B Version)
Units
Conditions/Comments
t1
0
ns min
Address to Write Setup Time
t2
0
ns min
Address Valid to Write Hold Time
t3
0
ns min
Chip Select to Write Setup Time
t4
0
ns min
Chip Select to Write Hold Time
t5
20
ns min
Write Pulse Width
t6
15
ns min
Data Setup Time
t7
4.5
ns min
Data Hold Time
t8
20
ns min
Write to
LDAC Setup Time
t9
20
ns min
LDAC Pulse Width
t10
20
ns min
CLR Pulse Width
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of
(VIL + VIH)/2. tr and tf should not exceed 1 s on any digital input.
2See Figure 1.
A/B
CS
WR
D7–D0
LDAC
CLR
t1
t2
t4
t3
t5
t6
t7
t8
t10
t9
Figure 1. Timing Diagram for Parallel Data Write
(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference;
all specifications TMIN to TMAX unless otherwise noted)
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