參數(shù)資料
型號(hào)： AD7262BSTZ-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/33頁(yè)
文件大?。?/td> 0K
描述： IC ADC 2CH 12BIT PGA/COM 48LQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 120mW
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)差分，單極
AD7262
Rev. 0 | Page 16 of 32
The two diodes provide ESD protection. Care must be taken to
ensure that the analog input signals never exceed the supply rails
by more than 300 mV. Exceeding 300 mV causes these diodes to
become forward-biased and to start conducting current into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part. The C1 capacitors in
Figure 24 are typically 5 pF and can primarily be attributed to
pin capacitance.
C1
VIN–
VDD
C1
VIN+
VOUT–
VOUT+
VDD
AMP
07
60
6-
02
4
Figure 24. Analog Input Structure
The AD7262/AD7262-5 can accept differential analog inputs from
×
Gain
V
REF
CM
2
to
×
+
Gain
V
REF
CM
2
Table 5 details the analog input range for the AD7262/AD7262-5
for the various PGA gain settings. Here, VREF = 2.5 V and VCM =
2.5 V (AVCC/2, with AVCC = 5 V).
Table 5. Analog Input Range for Various PGA Gain Settings
PGA Gain Setting
Analog Input Range for VIN+ and VIN
1
0.75 V to 3.25 V1
2
1.875 V to 3.125 V
3
2.083 V to 2.916 V
4
2.187 V to 2.813 V
6
2.292 V to 2.708 V
8
2.344 V to 2.656 V
12
2.396 V to 2.604 V
16
2.422 V to 2.578 V
24
2.448 V to 2.552 V
32
2.461 V to 2.539 V
48
2.474 V to 2.526 V
64
2.480 V to 2.520 V
96
2.487 V to 2.513 V
128
2.490 V to 2.510 V
1 For VCM = 2 V. If VCM = AVCC /2, the analog input range for VIN+ and VIN is 1.6 V
to 3.4 V.
When a full-scale step input is applied to either differential input
on the AD7262/AD7262-5 while the other analog input is held
at a constant voltage, 3 μs of settling time is typically required
prior to capturing a stable digital output code.
Transfer Function
The AD7262/AD7262-5 output is twos complement, and the
ideal transfer characteristic is shown in Figure 25. The designed
code transitions occur at successive integer LSB values (that is,
1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog
input range selected. The LSB size for the AD7262/AD7262-5 is
shown in the following equation:
×
×
+
×
4096
2
Gain
V
Gain
V
REF
CM
REF
CM
100...000
011...111
ADC
CO
DE
0V
100...001
100...010
011...110
000...001
111...111
000...000
ANALOG INPUT
NOTES
1. FULL-SCALE RANGE (FSR) = VIN+ – VIN–.
(VCM + (FSR/2)) – 1LSB
(VCM – (FSR/2)) + 1LSB
07
60
6-
02
5
Figure 25. Twos Complement Transfer Function
VDRIVE
The AD7262/AD7262-5 have a VDRIVE feature to control the
voltage at which the serial interface operates. VDRIVE allows the
ADC and the comparators to easily interface to both 3 V and
5 V processors. For example, when the AD7262/AD7262-5 are
operated with AVCC = 5 V, the VDRIVE pin can be powered from
a 3 V supply, allowing a large analog input range with low voltage
digital processors.
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