參數(shù)資料
型號(hào): AD7192BRUZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 25/41頁
文件大?。?/td> 0K
描述: IC ADC 24BIT 2CH SD 24-TSSOP
設(shè)計(jì)資源: Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 24
采樣率(每秒): 4.8k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極;2 個(gè)差分,雙極;4 個(gè)偽差分,單極;4 個(gè)偽差分,雙極
AD7192
Rev. A | Page 30 of 40
Continuous Conversion Mode
Continuous conversion is the default power-up mode. The
AD7192 converts continuously, and the RDY bit in the status
register goes low each time a conversion is complete. If CS is
low, the DOUT/RDY line also goes low when a conversion is
completed. To read a conversion, the user writes to the
communications register, indicating that the next operation is a
read of the data register. When the data-word has been read
from the data register, DOUT/RDY goes high. The user can
read this register additional times, if required. However, the
user must ensure that the data register is not being accessed at
the completion of the next conversion or else the new conversion
word is lost.
When several channels are enabled, the ADC continuously
loops through the enabled channels, performing one conversion
on each channel per loop. The data register is updated as soon
as each conversion is available. The DOUT/RDY pin pulses low
each time a conversion is available. The user can then read the
conversion while the ADC converts on the next enabled channel.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The status register
indicates the channel to which the conversion corresponds.
DIN
SCLK
DOUT/RDY
CS
0x58
DATA
07
82
2-
0
22
Figure 30. Continuous Conversion
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