參數(shù)資料
型號(hào): AD7148ACPZ-1500RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/57頁(yè)
文件大?。?/td> 0K
描述: IC CAP-TO-DGTL CONV PROG 16LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 電容性
觸摸面板接口: 2 線
輸入數(shù)/鍵: 8
分辨率(位): 16 b
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 250k
電壓基準(zhǔn): 內(nèi)部
電源電壓: 2.6 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
其它名稱(chēng): AD7148ACPZ-1500RL7DKR
AD7148
Rev. A | Page 40 of 56
Table 24. STAGEx_COMPLETE_INT_EN Register
Address
Data
Bit
Default
Value
Type
Mnemonic
Description
0x007
[0]
0
R/W
STAGE0_COMPLETE_INT_EN
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
[1]
0
R/W
STAGE1_COMPLETE_INT_EN
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
[2]
0
R/W
STAGE2_COMPLETE_INT_EN
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
[3]
0
R/W
STAGE3_COMPLETE_INT_EN
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
[4]
0
R/W
STAGE4_COMPLETE_INT_EN
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
[5]
0
R/W
STAGE5_COMPLETE_INT_EN
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
[6]
0
R/W
STAGE6_COMPLETE_INT_EN
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
[7]
0
R/W
STAGE7_COMPLETE_INT_EN
STAGE7 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
[15:8]
Unused
Set unused register bits to 0
Table 25. STAGEx_LOW_LIMIT_INT Register1
Address
Data
Bit
Default
Value
Type
Mnemonic
Description
0x008
[0]
0
R
STAGE0_LOW_LIMIT_INT
STAGE0 CDC conversion low limit interrupt result
1 = indicates STAGE0_LOW_THRESHOLD value exceeded
[1]
0
R
STAGE1_LOW_LIMIT_INT
STAGE1 CDC conversion low limit interrupt result
1 = indicates STAGE1_LOW_THRESHOLD value exceeded
[2]
0
R
STAGE2_LOW_LIMIT_INT
STAGE2 CDC conversion low limit interrupt result
1 = indicates STAGE2_LOW_THRESHOLD value exceeded
[3]
0
R
STAGE3_LOW_LIMIT_INT
STAGE3 CDC conversion low limit interrupt result
1 = indicates STAGE3_LOW_THRESHOLD value exceeded
[4]
0
R
STAGE4_LOW_LIMIT_INT
STAGE4 CDC conversion low limit interrupt result
1 = indicates STAGE4_LOW_THRESHOLD value exceeded
[5]
0
R
STAGE5_LOW_LIMIT_INT
STAGE5 CDC conversion low limit interrupt result
1 = indicates STAGE5_LOW_THRESHOLD value exceeded
[6]
0
R
STAGE6_LOW_LIMIT_INT
STAGE6 CDC conversion low limit interrupt result
1 = indicates STAGE6_LOW_THRESHOLD value exceeded
[7]
0
R
STAGE7_LOW_LIMIT_INT
STAGE7 CDC conversion low limit interrupt result
1 = indicates STAGE7_LOW_THRESHOLD value exceeded
[15:8]
Unused
Set unused register bits to 0
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
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