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參數(shù)資料
| 型號(hào)： | AD7111ABNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 0K |
| 描述： | IC DAC LOGARITHMIC 16-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD7111A Discontinuation 27/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | LOGDAC® |
| 位數(shù)： | 17 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 784 (CN2011-ZH PDF) |
AD7111/AD7111A
REV. 0
–7–
Another error arises from the output amplifier s input offset
voltage. The amplifier is operated with a fixed feedback resis-
tance, but the equivalent source impedance (the AD7111/
AD7111A output impedance) varies as a function of attenuation
level. This has the effect of varying thc “noise” gain of the
amplifier, thus creating a varying error due to amplifier offset
voltage. It is recommended that an amplifier with less than
50
V of input offset be used (such as the AD OP07 in dc appli-
cations. Amplifiers with higher offset voltage may cause audible
“thumps” in ac applications due to dc output changes.
The AD7111/AD7111A accuracy is specified and tested using
only the internal feedback resistor. Any gain error (i.e., mis-
match of RFB to the R-2R ladder) that may exist in the
AD7111/AD7111A D/A converter circuit results in a constant
attenuation error over the whole range. The AD7111/AD7111A
accuracy is specified relative to 0 dB attenuation, hence “Gain”
trim resistors—R1 and R2 in Figure 1—can be used to adjust
VOUT = VIN precisely (i.e., 0 dB attenuation) with input code
00000000. The accuracy and monotonic range specifications of
the AD7111/AD7111A are not affected in any way by this gain
trim procedure. For the AD7111/AD7111A L/C/U grades, suit-
able values for R1 and R2 of Figure 1 are R1 = 500
, R2 =
180
; for the K/B/T grades, suitable value are R1 = 1000 ,
R2 = 270
. For additional information on gain error the reader
is referred to the “CMOS DAC Application Guide,” available
from Analog Devices, Inc., Publication Number G872b–8–1/89.
Typical Performance Characteristics
6
0
5
3
1
2
0
5
4
3
2
INPUT VOLTAGE – Volts
I
DD
–
mA
V
IN APPLIED TO ALL DATA INPUTS
V
DD = +5V
T
A = +25°C
CS = WR = 0V
Figure 6. Typical Supply Current vs. Logic Input Level
0.4
–0.6
30
0.0
–0.4
3
–0.2
0
0.2
27
24
21
18
15
12
9
6
ATTENUATION – dB
ERROR
–
dB
* *
* * *
* *
*
* *
* * *
**
*
* ** *
**
*
* *
* * * * **
*
* * *
* *
*
V
DD = +5V
T
A = +25
°C
Figure 7. Typical Attenuation Error for 0.75 dB Steps
1.0
–1.0
078
0.5
–0.5
6
0.0
66
72
60
48
42
36
30
24
18
12
54
84
ATTENUATION – dB
ERROR
–
dB
T
A = +85
°C
T
A = +25
°C
DD
V
= +5V
Figure 8. Typical Attenuation Error for 3 dB Steps vs.
Temperature
Figure 9. Accuracy Specification for K/B/T Grade Devices
at TA = +25°C
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