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參數(shù)資料
| 型號： | AD7010 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口) |
| 中文描述： | 聯(lián)合紀(jì)律委員會DQPSK的CMOS基帶傳輸端口（的CMOS基帶傳輸口） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 257K |
| 代理商： | AD7010 |
AD7010
TRANSMT SECTIONTIMNG
REV. B
–4–
Parameter
Limit at T
A
= –40
°
C to +85
°
C
Units
Description
t
4
10
t
1
– 10
4097t
1
+ 70
10
t
1
– 10
t
1
+ 70
3t
1
+ 70
64t
1
32t
1
32t
1
50
0
3t
1
124t
1
7.5t
9
30t
1
10
10
ns min
ns max
ns max
ns min
ns max
ns max
ns
ns
ns
ns
ns min
ns min
ns max
ns max
ns
ns max
ns max
ns max
POWER Setup T ime.
t
5
t
6
MCLK rising edge, after POWER high, to READY rising edge.
BIN Setup T ime.
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
MCLK to READY low propagation delay.
MCLK rising edge, after BIN high, to first T xCLK rising edge.
T xCLK Cycle T ime.
T xCLK High T ime.
T xCLK Low T ime.
T xCLK falling edge to T xDAT A setup time.
T xCLK falling edge to T xDAT A hold time.
BIN low setup to last transmitted symbol after ramp down.
BIN low hold to last transmitted symbol after ramp down.
Ramp down cycle time after the last transmitted symbol.
Last T xCLK falling edge to READY rising edge.
Digital Output Rise T ime.
Digital Output Fall T ime.
MCLK
READY
BIN
TxCLK
TxDATA
Y
k
t
4
t
5
t
7
t
9
t
10
t
11
t
12
t
13
t
8
t
6
X
k
POWER
Figure 5. Transmit Timing at the Start of a Tx Burst
MCLK
READY
BIN
TxCLK
TxDATA
t
14
X
N+4
Y
N+4
X
N+5
Y
N+8
X
N+8
t
17
POWER
t
15
t
16
Figure 6. Transmit Timing at the End of a Tx Burst
(V
AA
= V
DD
= +5 V
6
10%; AGND = DGND = 0 V, f
MCLK
= 2.688 MHz. All specifications are
T
MN
to T
MAX
unless otherwse noted.)
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