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參數資料
| 型號： | AD6654BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 46/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 標準包裝： | 1 |
| 位數： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數據接口： | 串行，并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應商設備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 1 個差分，單極 |
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AD6654
Rev. 0 | Page 50 of 88
DESIRED SIGNAL LEVEL MODE
In this mode of operation, the AGC strives to maintain the
output signal at a programmable set level. The desired signal
level mode is selected by writing Logic 0 into the AGC clipping
error enable bit of the AGC control register. The loop finds the
square (or power) of the incoming complex data signal by
squaring I and Q and adding them.
The AGC loop has an average and decimate block. This average
and decimate operation takes place on power samples and
before the square root operation. This block can be pro-
grammed to average from 1 to 16,384 power samples, and the
decimate section can be programmed to update the AGC once
every 1 to 4,096 samples. The limitation on the averaging
operation is that the number of averaged power samples should
be a multiple of the decimation value (1×, 2×, 3×, or 4×).
The averaging and decimation effectively means that the AGC
can operate over averaged power of 1 to 16,384 output samples.
Updating the AGC once every 1 to 4,096 samples and operating
on average power facilitates the implementation of the loop
filter with slow time constants, where the AGC error converges
slowly and makes infrequent gain adjustments. It is also useful
when the user wants to keep the gain scaling constant over a
frame of data or a stream of symbols.
Due to the limitation that the number of average samples must
be a multiple of the decimation value, only the multiple
numbers 1, 2, 3, or 4 are programmed. This is set using the
AGC average samples word in the AGC average sample register.
These averaged samples are then decimated with decimation
ratios programmable from 1 to 4,096. This decimation ratio is
defined in the 12-bit AGC update decimation register.
The average and decimate operations are tied together and
implemented using a first-order CIC filter and FIFO registers.
Gain and bit growth are associated with CIC filters and depend
on the decimation ratio. To compensate for the gain associated
with these operations, attenuation scaling is provided before the
CIC filter.
This scaling operation accounts for the division associated with
the averaging operation as well as the traditional bit growth in
CIC filters. Because this scaling is implemented as a bit-shift
operation, only coarse scaling is possible. Fine scaling is imple-
mented as an offset in the request level, as explained later in this
section. The attenuation scaling, SCIC, is programmable from 0
to 14 using a 4-bit CIC scale word in the AGC average samples
register and is given by
(
)
[
]
AVG
CIC
N
M
ceil
S
×
=
2
log
where:
MCIC
is the decimation ratio (1 to 4,096).
NAVG
is the number of averaged samples programmed as a
multiple of the decimation ratio (1, 2, 3, or 4).
For example, if a decimation ratio MCIC is 1,000 and NAVG is 3
(decimation of 1,000 and averaging of 3,000 samples), then
the actual gain due to averaging and decimation is 3,000 or
69.54 dB (log2 (3000)). Because attenuation is implemented as a
bit-shift operation, only multiples of 6.02 dB attenuations are
possible. SCIC in this case is 12, corresponding to 72.24 dB. This
way, SCIC scaling always attenuates more than is sufficient to
compensate for the gain in the average and decimate sections
and, therefore, prevents overflows in the AGC loop. But it is
also evident that the SCIC scaling induces a gain error (the
difference between gain due to CIC and attenuation provided
by scaling) of up to 6.02 dB. This error should be compensated
for in the request signal level, as explained later in this section.
A logarithm to the Base 2 is applied to the output from the
average and decimate sections. These decimated power samples
are converted to rms signal samples by applying a square root
operation. This square root is implemented using a simple shift
operation in the logarithmic domain. The rms samples obtained
are subtracted from the request signal level R specified in the
AGC desired level register, leaving an error term to be
processed by the loop filter, G(z).
The user sets this programmable Request Signal Level R accord-
ing to the output signal level that is desired. The Request Signal
Level R is programmable from 0 dB to 23.99 dB in steps of
0.094 dB.
The request signal level should also compensate for errors, if
any, due to the CIC scaling, as previously explained in this
section. Therefore, the request signal level is offset by the
amount of error induced in CIC, given by
Offset
= 10 × log(MCIC × NAVG SCIC × 3.01 dB
where Offset is in dB.
Continuing the previous example, this offset is given by
Offset
= 72.24 69.54 = 2.7 dB
So the request signal level is given by
(
)
dBFS
094
.
0
094
.
0
×
=
Offset
DSL
ceil
R
where:
R
is the request signal level.
DSL
(desired signal level) is the output signal level that the user
desires.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD6654CBC | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數:12 采樣率（每秒）:1.8M 數據接口:并聯 轉換器數目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數目和類型:2 個單端，單極 |
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數:12 采樣率（每秒）:1.8M 數據接口:并聯 轉換器數目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數目和類型:2 個單端，單極 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關產品:- 已供物品:模塊 其它名稱:SER3796 |
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