參數(shù)資料
型號: AD632SD
廠商: Analog Devices Inc
文件頁數(shù): 2/13頁
文件大?。?/td> 0K
描述: IC PREC MULTIPLIER MONO 14-CDIP
標(biāo)準(zhǔn)包裝: 1
功能: 模擬乘法器/除法器
位元/級數(shù): 四象限
封裝/外殼: 14-CDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 14-CDIP
包裝: 管件
Data Sheet
AD632
Rev. D | Page 9 of 12
OPERATION AS A DIVIDER
Figure 9 shows the connection required for division. Unlike
earlier products, the AD632 provides differential operation on
both the numerator and the denominator, allowing the ratio of
two floating variables to be generated. Further flexibility results
from access to a high impedance summing input to Y1. As with
all dividers based on the use of a multiplier in a feedback loop,
the bandwidth is proportional to the denominator magnitude,
as shown in Figure 6.
The accuracy of the AD632 B-model is sufficient to maintain a
1% error over a 10 V to 1 V denominator range.
Figure 9. Basic Divider Connection
X1
+VS
X2
+VS
OUT
VOS
Z1
–VS
Z2
Y1
Y2
–VS
–15V
+15V
X INPUT
(DENOMINATOR)
+10V FS
+12V PK
Z INPUT
(NUMERATOR)
±10V FS, ±12V PK
OPTIONAL
SUMMING INPUT
±10V PK
+
+15V
–15V
2k
TO
200k
10 (Z2 – Z1)
(X1 – X2)
+ Y1
=
OUTPUT, ±12V PK
09040-
010
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