參數(shù)資料
型號(hào)： AD600ARZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/33頁(yè)
文件大?。?/td> 0K
描述： IC AMP VGA DUAL LN 50MA 16SOIC
標(biāo)準(zhǔn)包裝： 1,000
系列： X-AMP®
放大器類型： 可變?cè)鲆?br>
電路數(shù)： 2
轉(zhuǎn)換速率： 275 V/µs
-3db帶寬： 35MHz
電流 - 輸入偏壓： 350nA
電流 - 電源： 11mA
電流 - 輸出 / 通道： 50mA
電壓 - 電源，單路/雙路(±)： ±4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 帶卷 (TR)
AD600/AD602
Rev. F | Page 26 of 32
For the next 40 dB of control range, the gain of U1A remains
fixed at its maximum value of 41.07 dB and only the gain of
U1B is varied, while that of U2A remains at its minimum value
of 1.07 dB. In this interval, the fixed output noise of U1A is
amplified by the increasing gain of U1B, and the SNR
progressively decreases.
Once U1B reaches its maximum gain of 41.07 dB, its output
also becomes a gain-independent noise source; this noise is
presented to U2A. As the control voltage is further increased,
the gains of both U1A and U1B remain fixed at their maximum
value of 41.07 dB, and the SNR continues to decrease. Figure 56
clearly shows this because the maximum SNR of 90 dB is
extended for the first 40 dB of input signal before it starts to roll off.
This arrangement of staggered gains can be easily implemented
because, when the control inputs of the AD600 are overdriven,
the gain limits to its maximum or minimum values without side
effects. This eliminates the need for awkward nonlinear shaping
circuits that have previously been used to break up the gain
range of multistage AGC amplifiers. The precise values of the
AD600’s maximum and minimum gain (not 0 dB and +40 dB
but 1.07 dB and +41.07 dB) explain the rather odd values of
the offset values that are used.
The optimization of the output SNR is of obvious value in AGC
systems. However, in applications where these circuits are
considered for their wide range logarithmic measurement
capabilities, the inevitable degradation of the SNR at high gains
need not seriously impair their utility. In fact, the bandwidth of
the circuit shown in Figure 47 was specifically chosen to improve
measurement accuracy by altering the shape of the log error
curve at low signal levels (see Figure 53).
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