Reducing AICC Current Requirements Th" />
參數(shù)資料
型號： AD5755-1ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/52頁
文件大?。?/td> 0K
描述： IC DAC 16BIT SERIAL 64LFCSP
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
特色產(chǎn)品： AD5755 / AD5755-1 / AD5757 DACs
標準包裝： 1
設(shè)置時間： 11µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，4 電壓
采樣率（每秒）： *
Data Sheet
AD5755-1
Rev. E | Page 45 of 52
Reducing AICC Current Requirements
There are two main methods that can be used to reduce the
AICC current requirements. One method is to add an external
compensation resistor, and the other is to use slew rate control.
Both of these methods can be used in conjunction.
A compensation resistor can be placed at the COMPDCDC_x pin
in series with the 10 nF compensation capacitor. A 51 k exter-
nal compensation resistor is recommended. This compensation
increases the slew time of the current output but eases the AICC
transient current requirements. Figure 83 shows a plot of AICC
current for a 24 mA step through a 1 k load when using a
51 k compensation resistor. This method eases the current
requirements through smaller loads even further, as shown in
0
4
12
8
16
24
20
28
32
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
09226-
185
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
mA
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
Figure 83. AICC Current vs. Time for 24 mA Step Through 1 k Load
with External 51 k Compensation Resistor
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
500 LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
09226-
186
0
4
12
8
16
24
20
28
32
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
mA
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
Figure 84. AICC Current vs. Time for 24 mA Step Through 500 Load
with External 51 k Compensation Resistor
Using slew rate control can greatly reduce the AVCC supplies
current requirements, as shown in Figure 85. When using slew
rate control, attention should be paid to the fact that the output
cannot slew faster than the dc-to-dc converter. The dc-to-dc
converter slews slowest at higher currents through large (for
example, 1 k) loads. This slew rate is also dependent on the
configuration of the dc-to-dc converter. Two examples of the
dc-to-dc converter output slew are shown in Figure 83 and
Figure 84 (VBOOST corresponds to the dc-to-dc converter’s output
voltage).
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
09226-
187
0
1
2
3
4
5
6
I O
UT
_
x
CURRE
NT
(
mA
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
Figure 85. AICC Current vs. Time for 24 mA Step Through 1 k Load
with Slew Rate Control
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