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AD5722R/AD5732R/AD5752R
Rev. D | Page 6 of 32
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V; AVSS = 4.5 V to 16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V external; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at tMIN, tMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5
13
ns min
SCLK falling edge to SYNC rising edge
t6
100
ns min
Minimum SYNC high time (write mode)
t7
7
ns min
Data setup time
t8
2
ns min
Data hold time
t9
20
ns min
LDAC falling edge to SYNC falling edge
t10
130
ns min
SYNC rising edge to LDAC falling edge
t11
20
ns min
LDAC pulse width low
t12
10
μs typ
DAC output settling time
t13
20
ns min
CLR pulse width low
t14
2.5
μs max
CLR pulse activation time
ns min
SYNC rising edge to SCLK rising edge
40
ns max
SCLK rising edge to SDO valid (CL SDO5 = 15 pF) t17
200
ns min
Minimum SYNC high time (readback/daisy-chain mode)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Daisy-chain and readback mode.
5 CL SDO = capacitive load on SDO output.